Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: There is provided a method of charging an array of micro-capillaries. The micro-capillaries have at least one end that is open for fluid communication. The method includes the steps of: (a) filling the array of micro-capillaries with an assay liquid; (b) controllably evaporating at least some of the assay liquid to remove it from the micro-capillary and create a void space in each of the capillaries between the assay liquid and the open end; and (c) filling the void space with a liquid that is immiscible with said assay liquid. There is also provided a use of the disclosed method and a device for charging an array of micro-capillaries.

Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Abstract: A method and system receive consumer media consumption data and dynamically prioritize the allocation of marketing resources amongst a variety of media intellectual property (IP) assets and for a variety of media IP asset managers and owners to run automated targeted marketing campaigns. The system identifies patterns in consumer media consumption using a statistical model which detects media IP assets demonstrating a high likelihood of realizing an efficient marketing opportunity. The efficiency of a marketing opportunity is evaluated using a statistical model based on the identification of customers who are most likely to increase the frequency with which they stream the assets after being exposed to them via a marketing action in addition to the projected costs of reaching this audience. The system automatically constructs a marketing campaign. The campaign is presented to the asset manager/owner in a graphical user interface (GUI) which enables the option to purchase and execute the marketing actions.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.

Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact and a first bonding alignment mark. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact and a second bonding alignment mark. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface.

Abstract: Embodiments of methods for forming three-dimensional (3D) memory devices are disclosed. In an example, a peripheral device is formed on a first substrate. A first interconnect layer is formed above the peripheral device on the first substrate. A dielectric stack including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack is formed on a second substrate. A second interconnect layer is formed above the memory strings on the second substrate. The first substrate and the second substrate are bonded, so that the first interconnect layer is below and in contact with the second interconnect layer. The second substrate is thinned after the bonding. A memory stack is formed below the thinned second substrate and including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs.

Abstract: Embodiments of methods for forming three-dimensional (3D) memory devices are disclosed. In an example, a peripheral device is formed on a first substrate. A first interconnect layer is formed above the peripheral device on the first substrate. A dielectric stack including a plurality of dielectric/sacrificial layer pairs and a plurality of memory strings each extending vertically through the dielectric stack is formed on a second substrate. A second interconnect layer is formed above the memory strings on the second substrate. The first substrate and the second substrate are bonded, so that the first interconnect layer is below and in contact with the second interconnect layer. The second substrate is thinned after the bonding. A memory stack is formed below the thinned second substrate and including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, sacrificial layers in the dielectric/sacrificial layer pairs.

Abstract: The present invention provides a polishing roll capable of, for example, realizing three-dimensional polishing of hard materials such as sapphire glass at a high removal amount. The polishing roll is a cylindrical polishing roll capable of rotating about a central axis, characterized in that the polishing roll includes a core part serving as a central axis to which torque is applied, an intermediate part having a cross-section concentric with the core part, and a polishing part disposed on the outer peripheral surface of the intermediate part, and the intermediate part is made of a cushion material that is softer than the polishing part.

Abstract: Disclosed are peptidomimetic macrocycles comprising a helix, such as an alpha helix, and methods of using such macrocycles for the treatment of disease such as cancer. In other aspects, the peptidomimetic macrocycle comprises an ?,?-disubstituted amino acid, or may comprise a crosslinker linking the ?-positions of at least two amino acids or at least one of said two amino acids may be an ?,?-disubstituted amino acid. Further included is the targeting of components of the Wnt signaling pathway such as the Tcf4-/3-catenin complex.

Abstract: In some examples, a window in an image may be identified. At least one property of the window may be identified. Based on the at least one property, whether the window is an error block may be determined.

Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Abstract: Techniques described herein include an event notification processing platform configured to process large-scale event notifications in relative real time. The platform may receive event notifications from multiple sources and publish them to an event stream, or log. The platform may subsequently process each notification at a processing module according to one or more sets of rules and the processed information may be made available via a data store. Rule sets may be selected based on the type of event received by the platform. A backup data store may record event notifications as they are received or at periodic intervals. Event notification data may also be stored at multiple levels of the platform, so that in the case of a failure of one or more components of the platform, data may continue to be processed.

Abstract: There is provided a method of charging an array of micro-capillaries. The micro-capillaries have at least one end that is open for fluid communication. The method includes the steps of: (a) filling the array of micro-capillaries with an assay liquid; (b) controllably evaporating at least some of the assay liquid to remove it from the micro-capillary and create a void space in each of the capillaries between the assay liquid and the open end; and (c) filling the void space with a liquid that is immiscible with said assay liquid. There is also provided a use of the disclosed method and a device for charging an array of micro-capillaries.

Abstract: The present invention provides novel peptidomimetic macrocycles and methods of using such macrocycles for the treatment of disease.

Abstract: Disclosed are peptidomimetic macrocycles comprising a helix, such as an alpha helix, and methods of using such macrocycles for the treatment of disease such as cancer. In other aspects, the peptidomimetic macrocycle comprises an ?,?-disubstituted amino acid, or may comprise a crosslinker linking the ?-positions of at least two amino acids or at least one of said two amino acids may be an ?,?-disubstituted amino acid. Further included is the targeting of components of the Wnt signaling pathway such as the Tcf4-/3-catenin complex.