Abstract: A non-volatile memory system tests for a voltage leak in any of multiple planes using a voltage being ramped up on selected word lines in the multiple planes. If no voltage leak is detected, then the system concurrently programs data into memory cells connected to the selected word lines in the multiple planes. If a voltage leak is detected in any of the planes, then the system separately tests each plane for the voltage leak at its respective selected word line in order to determine which plane is the source of the voltage leak, and then concurrently programs data into memory cells connected to the selected word lines in planes without the detected voltage leak while isolating the plane with the detected voltage leak.

Abstract: To reduce Icc spikes during the operation of a non-volatile memory device, a distributed temperature sensing system individually monitors each plane of a memory die during memory operations. Icc levels during a memory operation are temperature dependent. By monitoring the temperature of the individual memory planes during an operation, the bias levels for performing the operation can be changed during the course of that operation in order to reduce Icc spikes during the operation. For example, during a write operation if the temperature increase of a plane exceeds a threshold during earlier programming loops, the bias conditions, such as word line or bit line bias voltages, can be altered for later programming loops of the write operation.

Abstract: Different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.

Abstract: A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means ramps up and applies a read voltage to unselected ones of the word lines while applying verification pulses of program verify voltages each associated with one of the plurality of data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the verify voltages associated with the plurality of data states targeted during a program-verify operation. The control means delays ramping of at least one of the selected ones of the word lines and the unselected ones of the word lines by a predetermined period of time in response to the memory apparatus operating in a predetermined mode.

Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.

Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

Abstract: An apparatus is provided that includes a block including a word line coupled to a plurality of memory cells, and a control circuit coupled to the word line. The control circuit is configured to program the plurality of memory cells by applying program pulses to the word line in a plurality of program loops, determining a first count of a number of the program loops used to complete programming a first subset of the plurality of memory cells to a first programmed state, first comparing the first count to a corresponding first lower limit and a corresponding first upper limit, and determining whether programming the plurality of memory cells has failed based on a result of the first comparing step.

Abstract: Technology is disclosed herein for a storage system that mitigates erase saturation when erasing memory cells. If erase does not pass after a number of erase loops, the storage system applies a program pulse to memory cells on faster to erase NAND strings. However, memory cells on slower to erase NAND strings are inhibited from programming. The program pulse increases the Vt of memory cells on the faster to erase NAND strings. Then, another erase loop is performed. The process may continue with additional loops, with each loop programming the memory cells on the faster to erase NAND strings followed by an erase pulse to all NAND strings and erase verify. Over-erase of the memory cells on the faster to erase NAND strings is therefore prevented. Moreover, slower to erase NAND strings that may otherwise be a bottleneck do not prevent successful completion of the erase.

Abstract: Technology is disclosed herein for a storage system and method for multi-stage discharge of a read pass voltage. In an aspect, the voltage on unselected word lines is reduced from the read pass voltage to an intermediate voltage during a first stage near the end of a read operation. A read reference voltage on the selected word line may be changed (e.g., increased) to the intermediate voltage during the first stage. During a second stage the voltage on the unselected word lines may be reduced from the intermediate voltage to a final voltage. The voltage on the selected word line may also be decreased during the second stage from the intermediate voltage to the final voltage. The multi-stage discharge of the read pass voltage may reduce peak current consumption (e.g., peak Icc) in a final portion of the read operation.

Abstract: To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.

Abstract: A non-volatile memory system is configured to permanently erase a single file from a block of non-volatile memory cells. That block is storing programmed data including the single file to be erased and other programmed data. The single file is erased from the block such that the other programmed data in the block is not moved or otherwise disturbed.

Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

Abstract: A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system compares threshold voltages of the non-volatile memory cells to an intermediate reference voltage that is greater than the erase verify reference voltage and determines an amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage. The Allowed Bit Count is increased (during the erase process) by the amount of non-volatile memory cells having threshold voltages greater than the intermediate reference voltage.

Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.

Abstract: To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some embodiments, the programming comprises applying doses of a programming signal and the gate to channel voltage differential is only created for a subset of the time periods between doses of the programming signal.