Abstract: A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.

Abstract: Technology for gate induced drain leakage (GIDL) erase of NAND strings. The drain-to-gate voltage of a source side select transistor (or transistors) is trimmed to compensate for different physical characteristics of the NAND strings in different regions of a memory system. The drain-to-gate voltage generates a GIDL current at the source end of a NAND string during a GIDL erase. The memory system uses different magnitudes for the drain-to-gate voltage applied to source side select transistor(s) on NAND strings in different regions of the memory system to provide for more uniform GIDL current during erase.

Abstract: A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises determining whether a number of memory cells connected to even word lines that have a different erase verify result than memory cells connected to odd word lines is greater than a defect test threshold. The system retires blocks from further use for storing host data that fail the odd/even compare process even if the block passes erase verification.

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

Abstract: A method includes performing, using a first artificial intelligence (AI) network, image processing based on input information to obtain a first image and image guidance information, the image guidance information comprising at least one of spatial correlation guidance information and semantic correlation guidance information; and performing, using a second AI network, resolution processing on the first image based on the image guidance information to obtain a second image.

Abstract: A memory device includes a plurality of memory cells and control circuitry configured to operate in both a quad-level cell (QLC) mode and a triple-level cell (TLC) mode. The control circuity is configured to, to operate in the QLC mode, perform at least one of a QLC programming operation and a QLC read operation on one or more of the plurality of memory cells, to operate in the TLC mode, perform a TLC programming operation on one or more of the plurality of memory cells, and selectively switch between the QLC mode and the TLC mode.

Abstract: The memory device includes a memory block with an array of memory cells that are arranged word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. During programming, the circuitry is configured to, in a program loop, apply a programming pulse at a programming voltage VPGM to a selected word line to program a plurality of the memory cells of the selected word line to a target data state. The circuitry is also configured to suspend the programming operation for a suspension duration and then resume the programming operation. Before a next program loop, the circuitry is further configured to increase a programming voltage VPGM by a step size that is determined based on the suspension duration and on the targeted data state.

Abstract: A memory apparatus includes memory cells connected to word lines and operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is coupled to the word lines and is configured to program the memory cells in a program operation. Following programming of the memory cells connected to specific ones of the word lines, the control means is also configured to apply a predetermined dummy read voltage to the specific ones of the word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the word lines determined based on an amount of the memory cells that are programmed.

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

Abstract: To reduce Icc spikes during the operation of a non-volatile memory device, different block decoding parameters can be used based on whether a block is open or closed. For blocks that are open or in other high Icc conditions, such as first read, the timing for the block decode control signals, the block decode voltage levels, or a combination of these can be used to lower Icc spikes.

Abstract: A memory system implemented on one or more die includes a power input line for the one or more die, a current detection circuit connected to the power input line such that the current detection circuit is configured to indicate whether current at the power input is greater than a reference current, and a control circuit connected to the power input line and the current detection circuit. The control circuit is also connected to a non-volatile memory structure comprising a plurality of non-volatile memory cells. The control circuit is configured to sense data from the non-volatile memory structure including lowering a voltage used during the sensing in response to the current detection circuit indicating that current at the power input line is greater than the reference current.

Abstract: A non-volatile memory comprises a plurality of non-volatile memory cells positioned in different regions of a block of non-volatile memory cells. Each region is connected to a different separate and independently controlled selection line so that each of the regions can be selected (e.g., one at a time) for a memory operation. To perform a read operation, the memory system is configured to apply a voltage to a selected word line and sequentially sense data from non-volatile memory cells positioned in the different regions without recharging the voltage applied to the selected word line.

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

Abstract: Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.

Abstract: An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by receiving a desired amount of variation from a baseline erase pulse parameter, generating a first erase pulse that includes the desired amount of variation from the baseline erase pulse parameter, and applying the first erase pulse to the block of memory cells. The desired amount of variation from the baseline erase pulse is selected to reduce erase-induced damage to the block of memory cells.

Abstract: A non-volatile memory is configured to transition blocks of non-volatile memory cells between full block mode and sub-block mode.

Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.

Abstract: When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.

Abstract: Technology is disclosed herein for a shallow erase for erase pool management. The memory system performs a shallow erase of a block of memory cells prior to placing the block in a shallow erase pool. The block may remain in the shallow erase pool for a substantial time with little to no risk of damage to the memory cells. The memory system completes the erase of the block at a later time. The memory system may select the block from the shallow erase pool when the system determines there is a need for another fully erased block. The erase voltage used for the shallow erase may be substantially lower in magnitude than the erase voltage used to complete the erase.