Patents by Inventor Jiahui Yuan

Jiahui Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NON-VOLATILE MEMORY WITH SUSPENSION PERIOD DURING PROGRAMMING
    Publication number: 20240006002
    Abstract: To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some embodiments, the programming comprises applying doses of a programming signal and the gate to channel voltage differential is only created for a subset of the time periods between doses of the programming signal.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiacen Guo, Jiahui Yuan
  • Non-volatile memory with staggered ramp down at the end of pre-charging
    Patent number: 11862249
    Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: January 2, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Fanqi Wu, Jiacen Guo, Jiahui Yuan
  • RELIABILITY IMPROVEMENT THROUGH DELAY BETWEEN MULTI-STAGE PROGRAMMING STEPS IN NON-VOLATILE MEMORY STRUCTURES
    Publication number: 20230420051
    Abstract: A method for multi-stage programming of a non-volatile memory structure, wherein the method comprises: (1) initiating a programming operation with respect to a memory block, (2) applying a programming algorithm to the memory block, wherein the programming algorithm comprises at least a first programming stage and a second programming stage, and (3) between the first programming stage and the second programming stage, applying a time delay according to a pre-determined amount of time. Further, the pre-determined amount of time may be defined as the amount of time that, according to a probabilistic function, permits de-trapping of any charges unintentionally trapped within a memory cell of the memory block as a result of the first programming stage.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Qing Cai, Henry Chin, Jiahui Yuan
  • DUMMY CELL RESISTANCE TUNING IN NAND STRINGS
    Publication number: 20230410906
    Abstract: An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation to program data memory cells. The control circuit is configured to apply a second dummy word line voltage to the one or more dummy word lines in a read operation to read the data memory cells.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Xiang Yang
  • BALANCING PEAK POWER WITH PROGRAMMING SPEED IN NON-VOLATILE MEMORY
    Publication number: 20230410911
    Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying withing the allowed peak Icc.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 21, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Towhidur Razzak, Jiahui Yuan, Deepanshu Dutta
  • NON-VOLATILE MEMORY WITH TUNING OF ERASE PROCESS
    Publication number: 20230395157
    Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Yanjie Wang
  • Non-volatile memory with adjusted bit line voltage during verify
    Patent number: 11837296
    Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: December 5, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Jiahui Yuan, Ohwon Kwon
  • MEMORY CELL GROUP READ WITH COMPENSATION FOR DIFFERENT PROGRAMMING SPEEDS
    Publication number: 20230368846
    Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jiacen Guo, Xiaochen Zhu, Xiang Yang, Lito De La Rama, Yi Song, Jiahui Yuan
  • NON-VOLATILE MEMORY WITH CONCURRENT SUB-BLOCK PROGRAMMING
    Publication number: 20230343395
    Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ke Zhang, Liang Li, Jiahui Yuan
  • Video sampling method and apparatus using the same
    Patent number: 11790655
    Abstract: A video sampling method, including sampling a video based on a sampling window to obtain a current sequence of sampled images; acquiring action parameters corresponding to the current sequence of sampled images; adjusting the sampling window according to the action parameters; and sampling the video based on the adjusted sampling window.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiahui Yuan, Wei Wen, Jianhua Fan
  • Non-volatile memory with updating of read compare voltages based on measured current
    Patent number: 11791001
    Abstract: A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: October 17, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yi Song, Jiahui Yuan, Dengtao Zhao
  • Non-volatile memory with reverse state program
    Patent number: 11790994
    Abstract: A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: October 17, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ming Wang, Liang Li, Jiahui Yuan
  • THREE-DIMENSIONAL MEMORY DEVICE INCLUDING AN ISOLATION-TRENCH ETCH STOP LAYER AND METHODS FOR FORMING THE SAME
    Publication number: 20230328973
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Ramy Nashed Bassely Said, Raghuveer S. Makala, Jiahui Yuan, Senaka Kanakamedala
  • MEMORY APPARATUS AND METHOD OF OPERATION USING STATE DEPENDENT STROBE TIER SCAN TO REDUCE PEAK ICC
    Publication number: 20230326530
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Chin-Yi Chen, Muhammad Masuduzzaman, Kou Tei, Deepanshu Dutta, Hiroyuki Mizukoshi, Jiahui Yuan, Xiang Yang
  • NON-VOLATILE MEMORY WITH ZONED CONTROL OF PROGRAMMING
    Publication number: 20230317169
    Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Xiaochen Zhu, Lito De La Rama, Yi Song, Jiacen Guo, Jiahui Yuan
  • VERIFY TECHNIQUES FOR CURRENT REDUCTION IN A MEMORY DEVICE
    Publication number: 20230307071
    Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Bai Pitner, Yu-Chung Lien, Ravi Kumar, Jiahui Yuan, Bo Lei, Zhenni Wan
  • NON-VOLATILE MEMORY WITH UPDATING OF READ COMPARE VOLTAGES BASED ON MEASURED CURRENT
    Publication number: 20230298678
    Abstract: A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Yi Song, Jiahui Yuan, Dengtao Zhao
  • LOW POWER MODE WITH READ SEQUENCE ADJUSTMENT
    Publication number: 20230290403
    Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jiahui Yuan, Kai Kirk, Yu-Chung Lien
  • Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines
    Patent number: 11758718
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 12, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada, Kazuki Isozumi
  • Obtaining threshold voltage measurements for memory cells based on a user read mode
    Patent number: 11756630
    Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Qianqian Yu, Jiahui Yuan, Loc Tu