Patents by Inventor Jiahui Yuan

Jiahui Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THREE-DIMENSIONAL MEMORY DEVICE INCLUDING AN ISOLATION-TRENCH ETCH STOP LAYER AND METHODS FOR FORMING THE SAME
    Publication number: 20230328973
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Ramy Nashed Bassely Said, Raghuveer S. Makala, Jiahui Yuan, Senaka Kanakamedala
  • MEMORY APPARATUS AND METHOD OF OPERATION USING STATE DEPENDENT STROBE TIER SCAN TO REDUCE PEAK ICC
    Publication number: 20230326530
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
    Type: Application
    Filed: April 7, 2022
    Publication date: October 12, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Chin-Yi Chen, Muhammad Masuduzzaman, Kou Tei, Deepanshu Dutta, Hiroyuki Mizukoshi, Jiahui Yuan, Xiang Yang
  • NON-VOLATILE MEMORY WITH ZONED CONTROL OF PROGRAMMING
    Publication number: 20230317169
    Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Xiaochen Zhu, Lito De La Rama, Yi Song, Jiacen Guo, Jiahui Yuan
  • VERIFY TECHNIQUES FOR CURRENT REDUCTION IN A MEMORY DEVICE
    Publication number: 20230307071
    Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Bai Pitner, Yu-Chung Lien, Ravi Kumar, Jiahui Yuan, Bo Lei, Zhenni Wan
  • NON-VOLATILE MEMORY WITH UPDATING OF READ COMPARE VOLTAGES BASED ON MEASURED CURRENT
    Publication number: 20230298678
    Abstract: A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Yi Song, Jiahui Yuan, Dengtao Zhao
  • LOW POWER MODE WITH READ SEQUENCE ADJUSTMENT
    Publication number: 20230290403
    Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Jiahui Yuan, Kai Kirk, Yu-Chung Lien
  • Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines
    Patent number: 11758718
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 12, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada, Kazuki Isozumi
  • Obtaining threshold voltage measurements for memory cells based on a user read mode
    Patent number: 11756630
    Abstract: Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: September 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Qianqian Yu, Jiahui Yuan, Loc Tu
  • CELSRC VOLTAGE SEPARATION BETWEEN SLC AND XLC FOR SLC PROGRAM AVERAGE ICC REDUCTION
    Publication number: 20230253049
    Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.
    Type: Application
    Filed: February 8, 2022
    Publication date: August 10, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Sarath Puthenthermadam, Jiahui Yuan
  • NON-VOLATILE MEMORY WITH ZONE BASED PROGRAM SPEED ADJUSTMENT
    Publication number: 20230245706
    Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 3, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Yi Song, Jiahui Yuan, Yanjie Wang
  • Modifying program and erase parameters for single-bit memory cells to improve single-bit/multi-bit hybrid ratio
    Patent number: 11705206
    Abstract: Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: July 18, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jia Li, Jiahui Yuan, Bo Lei
  • WORD LINE ZONE DEPENDENT PRE-CHARGE VOLTAGE
    Publication number: 20230223084
    Abstract: A memory device that uses different programming parameters base on the word line(s) to be programmed is described. The programming parameter PROGSRC_PCH provides a pre-charge voltage to physical word lines. In some instances, the PROGSRC_PCH voltage is decoupled, and a new PROGSRC_PCH represents an adjusted (e.g., increased) pre-charge voltage for a certain physical word line or word line zone (i.e., predetermined group of word lines). Using different PROGSRC_PCH voltages can limit or prevent Vt distribution window degradation, particularly for relatively low physical word lines. Additionally, the overall programming time and average current consumed can also be reduced.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 13, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Fanqi Wu, Jiahui Yuan
  • NON-VOLATILE MEMORY WITH DIFFERENTIAL TEMPERATURE COMPENSATION FOR BULK PROGRAMMING
    Publication number: 20230197168
    Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
    Type: Application
    Filed: December 13, 2021
    Publication date: June 22, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Dengtao Zhao, Sarath Puthenthermadam, Jiahui Yuan
  • NON-VOLATILE MEMORY WITH DATA REFRESH
    Publication number: 20230187000
    Abstract: A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Jiahui Yuan, Jun Wan, Deepanshu Dutta
  • NON-VOLATILE MEMORY WITH DIFFERENTIAL TEMPERATURE COMPENSATION FOR SUPER PAGE PROGRAMMING
    Publication number: 20230186996
    Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yi Song, Dengtao Zhao, Sarath Puthenthermadam, Jiahui Yuan
  • Sub-block programming mode with multi-tier block
    Patent number: 11664075
    Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 30, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Jiahui Yuan, Tomer Eliash
  • Isolating problematic memory planes to avoid neighbor plan disturb
    Patent number: 11657883
    Abstract: Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: May 23, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ke Zhang, Liang Li, Jiahui Yuan
  • NON-VOLATILE MEMORY WITH STAGGERED RAMP DOWN AT THE END OF PRE-CHARGING
    Publication number: 20230154538
    Abstract: In order to inhibit memory cells from programming and mitigate program disturb, the memory pre-charges channels of NAND strings connected to a common set of control lines by applying positive voltages to the control lines and applying voltages to a source line and bit lines connected to the NAND strings. The control lines include word lines and select lines. The word lines include an edge word line. The memory ramps down the positive voltages applied to the control lines, including ramping down control lines on a first side of the edge word line, ramping down the edge word line, and performing a staggered ramp down of three or more control lines on a second side of the edge word line. After the pre-charging, unselected NAND strings have their channel boosted to prevent programming and selected NAND strings experience programming on selected memory cells.
    Type: Application
    Filed: November 16, 2021
    Publication date: May 18, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Fanqi Wu, Jiacen Guo, Jiahui Yuan
  • SOFT ERASE PROCESS DURING PROGRAMMING OF NON-VOLATILE MEMORY
    Publication number: 20230154541
    Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Jiahui Yuan, Deepanshu Dutta
  • NON-VOLATILE MEMORY WITH ADJUSTED BIT LINE VOLTAGE DURING VERIFY
    Publication number: 20230120352
    Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.
    Type: Application
    Filed: October 19, 2021
    Publication date: April 20, 2023
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Jiahui Yuan, Ohwon Kwon