Abstract: Some embodiments provide an image sensor pixel comprising a junction field effect transistor (JFET) and a floating diffusion configured to act as the gate of the JFET. An image sensor may comprise a plurality of pixels, at least one pixel comprising floating diffusion region formed in a semiconductor substrate, a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion, and a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate comprising the floating diffusion region.

Abstract: A sensing device includes a light source to emit light, a light sensor to detect reflection of the emitted light and distance determination circuitry responsive to reflected-light detection within the light sensor. The light sensor includes a photodetector having a photocharge storage capacity in excess of one electron and an output circuit that generates an output signal responsive to light detection within the photodetector with sub-hundred nanosecond latency. The distance determination circuitry measures an elapsed time based on transition of the output signal in response to photonic detection within the photodetector and determines, based on the elapsed time, a distance between the sensing device and a surface that yielded the reflection of the emitted light.

Abstract: First and second readout circuits, each having a respective floating diffusion node, are coupled to a photodetection element within a pixel of an integrated-circuit image sensor. Following an exposure interval in which photocharge is accumulated within the photodetection element, a first portion of the accumulated photocharge is transferred from the photodetection element to the first floating diffusion node to enable generation of a first output signal within the first readout circuit, and a second portion of the accumulated photocharge is transferred from the photodetection element to the second floating diffusion node to enable generation of a second output signal within the second readout circuit. A digital pixel value is generated based on the first and second output signals.

Abstract: A sensing device includes a light source to emit light, a light sensor to detect reflection of the emitted light and distance determination circuitry responsive to reflected-light detection within the light sensor. The light sensor includes a photodetector having a photocharge storage capacity in excess of one electron and an output circuit that generates an output signal responsive to light detection within the photodetector with sub-hundred nanosecond latency. The distance determination circuitry measures an elapsed time based on transition of the output signal in response to photonic detection within the photodetector and determines, based on the elapsed time, a distance between the sensing device and a surface that yielded the reflection of the emitted light.

Abstract: Some embodiments of the present disclosure are directed to an image sensor pixel that is configured for gateless reset of a floating diffusion. Some embodiments are directed to an image sensor comprising a plurality of pixels, at least one pixel comprising a floating diffusion formed in a semiconductor substrate; a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion; and a reset drain formed in the semiconductor substrate and spaced away from the floating diffusion by an intervening semiconductor region having a dopant type opposite to the dopant type of the reset drain and the floating diffusion, wherein the reset drain is configured to selectively reset the electrostatic potential of the floating diffusion in response to a voltage pulse applied to the reset drain.

Abstract: Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.

Abstract: Some embodiments provide methods and apparatus for quantum random number generation based on a single bit or multi bit Quanta Image Sensor (QIS) providing single-photon counting over a time interval for each of an array of pixels of the QIS, wherein random number data is generated based on the number of photons counted over the time interval for each of the pixels.

Abstract: Some embodiments provide an image sensor pixel comprising a junction field effect transistor (JFET) and a floating diffusion configured to act as the gate of the JFET. An image sensor may comprise a plurality of pixels, at least one pixel comprising a floating diffusion region formed in a semiconductor substrate, a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion, and a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate comprising the floating diffusion region.

Abstract: Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.

Abstract: Some embodiments of the present disclosure are directed to an image sensor pixel that is configured for gateless reset of a floating diffusion. Some embodiments are directed to an image sensor comprising a plurality of pixels, at least one pixel comprising a floating diffusion formed in a semiconductor substrate; a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion; and a reset drain formed in the semiconductor substrate and spaced away from the floating diffusion by an intervening semiconductor region having a dopant type opposite to the dopant type of the reset drain and the floating diffusion, wherein the reset drain is configured to selectively reset the electrostatic potential of the floating diffusion in response to a voltage pulse applied to the reset drain.

Abstract: Some embodiments of the present disclosure provide a semiconductor-based photon-counting sensor comprising a metal-insulator-semiconductor internal photoemission (e.g., thermionic-emission) detector formed on and/or in a first surface of a semiconductor substrate, and at least one jot formed on and/or in a second side of a semiconductor substrate. The at least one MIS photoemission detector and the at least one jot are configured such that a photocarrier generated in response to a photon incident on the MIS thermionic-emission detector is readout by the at least one jot.

Abstract: Some embodiments provide an image sensor pixel comprising a junction field effect transistor (JFET) and a floating diffusion configured to act as the gate of the JFET. An image sensor may comprise a plurality of pixels, at least one pixel comprising a floating diffusion region formed in a semiconductor substrate, a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion, and a JFET having (i) a source and a drain coupled by a channel region, and (ii) a gate comprising the floating diffusion region.

Abstract: Some embodiments of the present disclosure are directed to an image sensor pixel that is configured for gateless reset of a floating diffusion. Some embodiments are directed to an image sensor comprising a plurality of pixels, at least one pixel comprising a floating diffusion formed in a semiconductor substrate; a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion; and a reset drain formed in the semiconductor substrate and spaced away from the floating diffusion by an intervening semiconductor region having a dopant type opposite to the dopant type of the reset drain and the floating diffusion, wherein the reset drain is configured to selectively reset the electrostatic potential of the floating diffusion in response to a voltage pulse applied to the reset drain.

Abstract: Image sensor pixels having low full-well capacity and high sensitivity for applications such as DIS, qDIS, single/multi bit QIS. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate. Image sensor may also comprise an array of pixels, wherein each pixel comprises: a vertical bipolar structure including an emitter, base, collector configured for storing photocarriers in the base; and a reset transistor coupled to the base, configured to be completely reset of all free carriers using the reset transistor. The emitter may be configured as a pinning layer to facilitate full depletion of the base. Such image sensor pixels may have a full well capacity less than that giving good signal-to-noise ratio (SNR).

Abstract: Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.

Abstract: Some embodiments provide an image sensor having a low capacitance floating diffusion node based on by reducing the width of the overlap between the floating diffusion region and the reset gate of the reset transistor that is configured to selectively reset the potential of the floating diffusion, so as to reduce the overlap capacitance therebetween. The reset gate may be tapered along its length so as to have a minimum width proximal to the FD and a maximum width distal to the floating diffusion, such as near or at a drain region of the reset transistor. The floating diffusion may be defined to have a width less than the minimum floating diffusion width that could be achieved by the minimum definable width of a photoresist window opening used for doping the FD region for the given fabrication process. Shallow trench isolation and/or compensation doping may be used for such definition of the floating diffusion.

Abstract: Image sensor pixels having low full-well capacity and high sensitivity for applications such as DIS, qDIS, single/multi bit QIS. Some embodiments provide an image sensor pixel architecture, comprises a transfer gate, a floating diffusion region both formed on a first surface of a semiconductor substrate and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially or entirely beneath the transfer gate. Image sensor may also comprise an array of pixels, wherein each pixel comprises: a vertical bipolar structure including an emitter, base, collector configured for storing photocarriers in the base; and a reset transistor coupled to the base, configured to be completely reset of all free carriers using the reset transistor. The emitter may be configured as a pinning layer to facilitate full depletion of the base. Such image sensor pixels may have a full well capacity less than that giving good signal-to-noise ratio (SNR).