Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.

Abstract: A super-junction MOS device with an integrated TMBS structure and a manufacturing method thereof are provided. The super-junction MOS device includes a main body. The TMBS structure is connected in parallel between at least two cells of the main body.

Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.

Abstract: Disclosed is a method for manufacturing a trench-type MOSFET, which comprises: providing a semiconductor structure, forming a trench in the semiconductor structure; forming a side oxide layer and dielectric layer in the trench; forming a shielding conductor in the trench; removing the hard mask; performing wet etching to remove the side oxide layer and dielectric layer; depositing an oxide layer from above the trench; etching the oxide layer to make an upper surface of the oxide layer lower than that of the shielding conductor; forming a gate dielectric layer and a gate conductor on the oxide layer, wherein the gate dielectric layer is located on an upper-portion side wall of the trench and separates the gate conductor from the semiconductor structure. By improving gate poly morphology, figure of merit of the device is optimized.

Abstract: Disclosed is a super-junction device, comprising a semiconductor substrate and a super-junction structure on a first surface of the semiconductor substrate. The super-junction structure includes first semiconductor pillars and second semiconductor pillars. The super-junction device has a cell region and a terminal region surrounding the cell region, the super-junction structure has a portion located in the cell region, and another portion located in the terminal region. The super-junction device further includes a guard ring located in the terminal region and surrounding the cell region, the guard ring includes doped regions extending segmentally and top-end portions of a first set of semiconductor pillars connecting the doped regions into a continuous ring. The top-end portions of the first set of semiconductor pillars in the guard ring are undoped, thus improving impurity distribution of the guard ring, charge balance in the terminal region, and voltage withstand performance of the super-junction device.

Abstract: Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

Abstract: Disclosed is a manufacturing method of a trench-type power device. The manufacturing method comprises: forming a drift region; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; forming a doped region and a well region of P type in the drift region by performing first ion implantation; forming a source region of N type in the well region by performing second ion implantation. The well region in which a dopant concentration gradually decreases with depth is formed by the first ion implantation, an upper part of the well region is inverted by the second ion implantation to form the source region. The doped region and well region can be formed by self-alignment in a common ion implantation step, improving power device performance, reducing numbers of process steps of ion implantation and masks, reducing manufacturing cost.

Abstract: Disclosed is a split-gate MOSFET and a manufacturing method, including: forming a first trench in a semiconductor layer; forming a second trench communicated with the first trench by using the first trench; forming a first dielectric layer in the second trench, a second dielectric layer in the first trench; forming a first conductor, located in the second trench, isolated from the semiconductor layer by the first dielectric layer; forming a third dielectric layer covering the first conductor; forming a second conductor, located in the first trench, isolated from the semiconductor layer by the second dielectric layer, the first conductor being isolated from the second conductor by the third dielectric layer; forming a body region adjacent to the first trench, the first trench has an inner diameter greater than that of the second trench. Thus, process window is expanded and beneficial to forming the third dielectric layer.

Abstract: Disclosed is a split-gate MOSFET and a manufacturing method, comprising: forming a cavity in a semiconductor layer; form a first trench based on the cavity; forming a second trench communicated with the first trench and extending in a same direction with the second trench; forming a first dielectric layer and a second dielectric layer; forming a first conductor located in the second trench and isolated from the semiconductor layer by the first dielectric layer; forming a third dielectric layer covering a surface of the first conductor; forming a second conductor located in the first trench, isolated from the semiconductor layer by the second dielectric layer, and isolated from the second conductor by the third dielectric layer; forming a body region adjacent to the first trench, wherein an inner diameter of the first trench is larger than an inner diameter of the second trench. The manufacturing method expands a process window.

Abstract: A super-junction semiconductor device with an enlarged process window for a desirable breakdown voltage includes: a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate. The epitaxial layer includes a first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer. A band gap of the first semiconductor layer is greater than a band gap of the second semiconductor layer. A super-junction structure is formed in the epitaxial layer, including at least one first epitaxial pillar of a first dopant type, and at least one second epitaxial pillar of a second dopant type. The first epitaxial pillar and the second epitaxial pillar are alternately arranged along a transverse direction. The epitaxial layer has a sandwich structure.

Abstract: A method of making a silicon carbide MOSFET device can include: providing a substrate with a first doping type; forming a patterned first barrier layer on a first surface of the substrate; forming a source region with a first doping type in the substrate; forming a base region with a second doping type and a contact region with a second doping type in the substrate, and forming a gate structure. The first barrier layer can include a first portion and a second portion, the first portion can include a semiconductor layer and a removable layer different from the semiconductor layer, and the second portion can only include the removable layer.

Abstract: The present disclosure provides a metal oxide semiconductor device and a method for manufacturing the same. The metal oxide semiconductor device includes a semiconductor substrate, a patterned field oxide layer, first JFET implantation regions and second JFET implantation regions. Active regions and gate regions are formed on an upper surface of the semiconductor substrate, each active region is surrounded by two or more of the gate regions, and the gate regions form a grid and some gate regions overlap to form gate intersections. The first JFET implantation regions are formed by implanting ions underneath the gate intersections of the upper surface of the semiconductor substrate. Orthogonal projections of the first JFET implantation regions and the field oxide layer onto the substrate don't overlap. The second JFET implantation regions are formed by implanting ions into the upper surface of the semiconductor substrate and located underneath the gate regions that are not gate intersections.

Abstract: A VDMOS device and a fabrication method thereof are provided. The device includes unit cells which jointly form a cellular structure. The cellular structure includes spaced-apart source regions and surrounding gate regions. Some gate regions overlap to form gate intersections comprising separation regions; the others form non-intersecting gate regions. Each unit cell has a JFET region corresponding in position to one non-intersecting gate region and a JFET shielding region corresponding in position to one gate intersection. The difference in doping concentrations of different types of dopants in the JFET shielding region surpasses difference in doping concentrations in the JFET regions and therefore depletion layers disposed along diagonals of the gate intersections expand and merge more easily, thereby increasing breakdown voltage along the diagonals. Therefore, the device exhibits enhanced voltage tolerance and stability.

Abstract: The present disclosure relates to a super-junction device and a manufacturing method thereof. In the manufacturing method, a first plurality of semiconductor pillars are formed in an epitaxial layer and a sacrificial stack is formed above the epitaxial layer. The sacrificial stack is used as a hard mask both for a body region and for a source region, and has a sidewall which controls a channel length of the super-junction device to reduce process fluctuation in different batches and improve reliability of the super-junction device.

Abstract: Disclosed is a split-gate power MOS device and a manufacturing method thereof. The method comprises: forming a trench in an epitaxial layer on a substrate; forming a first insulation layer on a surface of the epitaxial layer and in the trench; filling a cavity with polycrystalline silicon, performing back-etching; performing spin-coating on the first gate conductor layer to form a second insulation layer; forming a mask on the second insulation layer, removing a portion of the first insulation layer, to expose an upper portion of the trench; forming a gate oxide layer on a sidewall of the upper portion of the trench and the surface of the epitaxial layer; and forming a second gate conductor layer in the upper portion of the trench. According to the present disclosure, voltage withstand and electric leakage between the first gate conductor layer and the second gate conductor layer are reduced.

Abstract: A method of manufacturing a trench MOSFET can include: forming a trench extending from an upper surface of a semiconductor base layer to internal portion of the semiconductor base layer; forming a first insulating layer covering sidewall and bottom surfaces of the trench and the upper surface of the semiconductor base layer; forming a shield conductor filling a lower portion of the trench, where the first insulating layer separates the shield conductor from the semiconductor base layer; forming a second insulating layer covering a top surface of the shield conductor, where the first insulating layer separates the second insulating layer from the semiconductor base layer, and the first and second insulating layers conformally form a dielectric layer; and removing the dielectric layer located on the upper surface of the semiconductor base layer and located on the upper sidewall surface of the trench.

Abstract: Disclosed is a trench-type MOSFET and a method for manufacturing the same. The method comprises: forming a trench in a semiconductor substrate; forming a first insulating layer and a shielding conductor in the trench; forming an opening on two sides of the shielding conductor in the trench, wherein the opening is separated from the shielding conductor by the first insulating layer; forming a gate dielectric layer and a gate conductor in the opening, wherein the trench extends from an upper surface of the semiconductor substrate into the semiconductor substrate, the first insulating layer covers a sidewall and a bottom of the trench and separates the shielding conductor from the semiconductor substrate, the gate dielectric layer at least covers a sidewall of the opening. The method simplifies the process steps of forming the trench-type MOSFET compared with the prior art, and reduces process errors.

Abstract: A LDMOS transistor and manufacturing method includes: forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, and at least exposes part of the source region; forming a first conductive channel by using a sidewall as a mask, the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer.

Abstract: Disclosed a silicon carbide MOSFET device and manufacturing method thereof. The method includes: forming a patterned first barrier layer on an upper surface of the substrate; forming a base region of a second doping type extending from the upper surface to an inside of the substrate through oblique implantation in a first ion implantation process by using a first barrier layer as a mask; forming a source region of the first doping type in the substrate; forming a contact region of the second doping type in the substrate; and forming a gate structure, an implantation angle of the first ion implantation process is adjusted so that the base region extends below a part of the first barrier layer. The method of the present disclosure not only reduces one photoetching process and saves cost, but also realizes a short channel and reduces an on-resistance of the device.

Abstract: The present disclose relates to a SiC MOSFET device and a manufacturing method thereof. The method includes providing a semiconductor base of a first doping type; forming a patterned first barrier layer on an upper surface; forming a source region extending from the upper surface to the interior of the semiconductor base by taking the first barrier layer as a mask, wherein the source region is of the first doping type; etching a part of the first barrier layer to form a second barrier layer, and allowing anion implantation window of the second barrier layer to be larger than the ion implantation window of the first barrier layer; forming a first type base region by taking the second barrier layer as a mask, wherein the first type base region is of a second doping type; and forming a contact region of the second doping type.