Abstract: A method for generating dummy patterns includes providing a layout region having a layout pattern with a first density, inserting a plurality of first dummy patterns with a second density corresponding to the first density in the layout pattern, dividing the layout region into a plurality of sub-regions with a third density, adjusting a size of the first dummy pattern according to a difference between the second density and the third density, and outputting the layout pattern and the first dummy patterns on a photomask.

Abstract: The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Abstract: A photo alignment process and a liquid crystal display using the same are provided. The photo alignment process includes the following steps. A photo alignment material layer is formed on a substrate. The photo alignment material layer is irradiated by a linearly polarized light. A surface of the photo alignment material layer is a first plane. A wave vector of the linearly polarized light is a K vector. A second plane is constructed from a normal vector of the first plane and the K vector. A polarization direction of the linearly polarized light is neither perpendicular nor parallel to the second plane.

Abstract: A liquid crystal display (LCD) structure is provided. A first alignment layer and a first electrode layer are disposed on a liquid crystal layer. A second electrode layer and a second alignment layer disposed under the liquid crystal layer. The first alignment layer and the second alignment layer respectively have a plurality of alignment areas with different aligning directions. At least one of the first electrode layer and the second electrode layer includes a substrate material and a plurality of openings, and at least includes a plurality of electrode areas. The boundaries of the electrode areas correspond to the boundaries of the alignment areas. The directions of the openings in the electrode areas are between the aligning directions of the corresponding alignment areas of the first alignment layer and the second alignment layer.

Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.

Abstract: The semiconductor device package includes a conformal shield layer applied to the exterior surface of the encapsulant. and an internal fence or separation structure embedded in the encapsulant. The fence separates the package into various compartments. with each compartment containing at least one die. The fence thus suppresses EMI between adjacent packages. The package further includes a ground path connected to the internal fence and conformal shield.

Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.

Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.

Abstract: A chip module and a fabricating method thereof are provided. Firstly, a substrate is provided. Next, a chip is assembled on the substrate and electrically connected with the substrate. Afterward, a plurality of passive units is assembled on the substrate in the style of encircling the chip. Then, a first glue structure is filled between the passive units so that an encircled area is defined by the first glue structure and the passive units. Then, a second glue structure is filled in the encircled area so that the chip is covered by the second glue structure.

Abstract: A substrate with a multi-domain vertical alignment pixel structure is provided. The substrate is opposite to a counter substrate with a common electrode, and a liquid crystal layer is disposed between the substrate and the counter substrate. The substrate includes a scan line and a data line, an active device, first and second patterned pixel electrodes and a voltage drop layer. Wherein, the first patterned pixel electrode provides a first electrical field to the liquid crystal layer, and the second patterned pixel electrode provides a second electrical field to the liquid crystal layer. The voltage drop layer makes the first electrical field smaller than the second electrical field.

Abstract: The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield.

Abstract: A liquid crystal (LC) display panel including a lower substrate with pixel structures, an upper substrate, and an LC layer is provided. Each of the pixel structures includes a transistor and a pixel electrode. The pixel electrode includes first and second pixel electrodes insulated from each other, respectively including a first pattern and a second pattern that different and complementary to each other. Each of the first pixel electrode and the second pixel electrode has at least a trunk with a width smaller than or equal to 10 microns and a plurality of branches. The LC layer is positioned between the upper and the lower substrates and includes a plurality of LC molecules and a plurality of polymers, which are formed on surfaces of at least one of the upper and the lower substrates to cause the plurality of LC molecules to have a pretilt angle.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Abstract: An image sensor package includes a substrate, a sensor chip, a frame, a lens element and at least a pair of guide pins. The sensor chip is mounted on the substrate, and has two opposite sides and a sensing region, which has a sensing region central axis. The frame is mounted on the substrate, and has an aperture and an inner space with the sensor chip disposed therein. The lens element is disposed inside the aperture and has a lens central axis. The guide pins locate oppositely inside the inner space of the frame with an interval between the tips of the guide pins substantially identical to the distance between the opposite sides of the sensor chip, wherein the central line of the interval between the tips of the guide pins defines a positioning line, which substantially coincides with the lens central axis; wherein the tip of each guide pin is aligned with one of the opposite sides of the sensor chip such that the positioning line is substantially coincided with the sensing region central axis.

Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.

Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.

Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.

Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.