Patents by Inventor Jian-Dong Du

Jian-Dong Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220066641
    Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 3, 2022
    Applicant: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Patent number: 11210028
    Abstract: The present invention discloses a method for accessing a flash memory module, wherein the flash memory module comprises a plurality of block, each block is implemented by a plurality of word lines, and each word line comprises a plurality of memory cells supporting a plurality of states. The method comprises the steps of: reading the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells; determining a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information; reading the memory cells of a second word line to obtain readout information of the second word line; and using the target decoding flow to decode the readout information of the second word line.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 28, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Pi-Ju Tsai
  • Patent number: 11210209
    Abstract: The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the method includes the steps of: using a time management circuit to generate current time information; when data is written into any one of the blocks, recording the time information generated by the time management circuit; and determining at least one specific block according to quantity of invalid pages within each block and the time information of each block.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Pi-Ju Tsai, Tsung-Chieh Yang
  • Patent number: 11175841
    Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 16, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Publication number: 20210334039
    Abstract: The present invention discloses a method for accessing a flash memory module, wherein the flash memory module comprises a plurality of block, each block is implemented by a plurality of word lines, and each word line comprises a plurality of memory cells supporting a plurality of states. The method comprises the steps of: reading the memory cells of at least a first word line of a specific block of the plurality of blocks to obtain a cumulative distribution information of the states of the memory cells; determining a target decoding flow selected from at least a first decoding flow and a second decoding flow according to the cumulative distribution information; reading the memory cells of a second word line to obtain readout information of the second word line; and using the target decoding flow to decode the readout information of the second word line.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Inventors: Jian-Dong Du, Pi-Ju Tsai
  • Publication number: 20210318953
    Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Publication number: 20210248036
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: April 28, 2021
    Publication date: August 12, 2021
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 11074174
    Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 27, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Patent number: 11030042
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20200310648
    Abstract: A method for use in management of a flash memory module is provided. The flash memory module has a plurality of blocks, wherein a portion of the blocks belong to a spare pool. The method includes: preserving at least one erased block in the spare pool for a write operation; monitoring an erasing period regarding the at least one erased block; and performing a replacement operation to replace the at least one erased block when the erase time exceeds a threshold.
    Type: Application
    Filed: January 7, 2020
    Publication date: October 1, 2020
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Publication number: 20200242026
    Abstract: The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the method includes the steps of: using a time management circuit to generate current time information; when data is written into any one of the blocks, recording the time information generated by the time management circuit; and determining at least one specific block according to quantity of invalid pages within each block and the time information of each block.
    Type: Application
    Filed: November 18, 2019
    Publication date: July 30, 2020
    Inventors: Jian-Dong Du, Pi-Ju Tsai, Tsung-Chieh Yang
  • Publication number: 20200242024
    Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a timer. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the timer is used to generate time information. In the operations of the flash memory controller, the microprocessor refers to the time information to perform dummy read operations upon at least a portion of the blocks, wherein the dummy read operations are not triggered by read commands from a host device.
    Type: Application
    Filed: November 13, 2019
    Publication date: July 30, 2020
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Tsung-Chieh Yang
  • Publication number: 20200242025
    Abstract: The present invention provides a flash memory controller, wherein the flash memory controller is arranged to access a flash memory module, and the flash memory controller includes a ROM, a microprocessor and a time-management circuit. The ROM stores a program code, the microprocessor is configured to execute the program code to control the access of the flash memory module, and the time-management circuit is configured to generate current time information. In the operations of the flash memory controller, when the microprocessor writes data into last pages of a specific block of the flash memory module, the microprocessor writes the time information generated by the time-management circuit into one of the last pages of the specific block.
    Type: Application
    Filed: November 13, 2019
    Publication date: July 30, 2020
    Inventors: Jian-Dong Du, Chia-Jung Hsiao, Pi-Ju Tsai
  • Publication number: 20200233745
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20200225876
    Abstract: The present invention proposes a method for managing a plurality of memory units in a flash memory module. The method includes: creating a programed timestamp corresponding to each first memory unit according to a data-written time of said each first memory unit; selecting a corresponding read-retry table for performing a read operation upon said each first memory unit according to the programed timestamp of said each first memory unit; and performing a first refresh operation according to program timestamps of first memory units that have been written with data.
    Type: Application
    Filed: January 1, 2020
    Publication date: July 16, 2020
    Inventors: Jian-Dong Du, Pi-Ju Tsai, Tsung-Chieh Yang
  • Patent number: 10713115
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 10630316
    Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: April 21, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Publication number: 20190089374
    Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
    Type: Application
    Filed: November 18, 2018
    Publication date: March 21, 2019
    Inventors: Tsung-Chieh Yang, Jian-Dong Du
  • Publication number: 20190073263
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 7, 2019
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 10164656
    Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Jian-Dong Du