Patents by Inventor Jian-Dong Du

Jian-Dong Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157098
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: December 18, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20180285195
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 10025662
    Abstract: A method used in a flash memory module having a plurality of storage blocks is disclosed. Each storage block can be used as a first block or a second block wherein a cell of the first block is arranged for storing data of 1 bit and a cell of the second block is arranged for storing data of at least 2 bits. The method includes: classifying data to be programmed into a plurality of groups of data; executing error code encoding to generate a corresponding parity check code to store the groups of data and the corresponding parity check code to at least one block of first blocks; and after completing storing the groups of data, performing an internal copy operation upon the groups of data and the corresponding parity check code from the at least one block of the first blocks to at least one second block.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 17, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 10019314
    Abstract: A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 10, 2018
    Assignee: Silicon Motion Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20180143877
    Abstract: A method used in a flash memory module having a plurality of storage blocks is disclosed. Each storage block can be used as a first block or a second block wherein a cell of the first block is arranged for storing data of 1 bit and a cell of the second block is arranged for storing data of at least 2 bits. The method includes: classifying data to be programmed into a plurality of groups of data; executing error code encoding to generate a corresponding parity check code to store the groups of data and the corresponding parity check code to at least one block of first blocks; and after completing storing the groups of data, performing an internal copy operation upon the groups of data and the corresponding parity check code from the at least one block of the first blocks to at least one second block.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20180143876
    Abstract: A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.
    Type: Application
    Filed: January 19, 2018
    Publication date: May 24, 2018
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20170288698
    Abstract: A method for determining when to end a bit flipping algorithm during hard decision soft decoding in a low density parity check (LDPC) decoder includes: selecting a certain number of iterations as a first threshold; when the first threshold is reached, determining a highest variable node codeword for each iteration performed so far; comparing the highest variable node codewords with a second threshold; and when the value of the highest variable node codewords is less than or equal to the second threshold, ending the bit flipping algorithm.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Inventor: Jian-Dong Du
  • Publication number: 20170288699
    Abstract: A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Tsung-Chieh Yang, Jian-Dong Du