Patents by Inventor Jian-Guo Chen

Jian-Guo Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10537835
    Abstract: A fully automatic magnetic filter includes an apparatus barrel, magnetic rollers, scrapers, and a motor. The number of the magnetic rollers is four and corresponds to the number of the scrapers. The magnetic rollers are located in the apparatus barrel, and each includes an outer layer and an inner core. The outer layer is sleeved onto the inner core. The inner core has a magnetic region and a non-magnetic region. The outer layers of the magnetic rollers are driven and connected through a gear. The outer layer of one of the magnetic rollers is connected with the motor and driven by the motor. Each scraper corresponds to the outer layer of a corresponding one of the magnetic rollers. When the iron filings adsorbed on the outer layer are rotated to the non-magnetic region, the iron filings can be scraped off by the scrapers.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 21, 2020
    Assignee: UNIVERSAL FILTRATION (SHANGHAI) CO., LTD.
    Inventor: Jian Guo Chen
  • Publication number: 20190370950
    Abstract: A defect displaying method is provided in the disclosure. The method comprises acquiring defect group information from an image of a wafer, wherein the defect group information includes a set of correlations between a plurality of defects identified from the image and one or more corresponding assigned defect types and displaying at least some of the plurality of defects according to their corresponding assigned defect types.
    Type: Application
    Filed: January 18, 2018
    Publication date: December 5, 2019
    Inventors: Wei FANG, Cho Huak TEH, Ju Hao CHIEN, Yi-Ying WANG, Shih-Tsung CHEN, Jian-Min LIAO, Chuan LI, Zhaohui GUO, Pang-Hsuan HUANG, Shao-Wei LAI, Shih-Tsung HSU
  • Publication number: 20190334514
    Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.
    Type: Application
    Filed: July 7, 2016
    Publication date: October 31, 2019
    Inventors: DAI-GUO XU, GANG-YI HU, RU-ZHANG LI, JIAN-AN WANG, GUANG-BING CHEN, YU-XIN WANG, DONG-BING FU, TAO LIU
  • Patent number: 10408246
    Abstract: A receiving device for an electronic device, to hold a stylus, includes a top member, a bottom member, and a connection member. The bottom member faces the top member, the connection member is arranged between the top member and the bottom member. A clamping member and a receiving member are formed between the top member, the bottom member, and the connection member. The clamping member faces away from the receiving member, the clamping member is clamped onto an electronic device, the receiving member receives a stylus.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 10, 2019
    Assignees: Fu Tai Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Lei Hu, Chia-Jui Hu, Hao-Yuan Huang, Yen-Yu Chen, Chun-Kai Peng, Jian-Guo Wu, Xin Yang
  • Publication number: 20190160402
    Abstract: A fully automatic magnetic filter includes an apparatus barrel, magnetic rollers, scrapers, and a motor. The number of the magnetic rollers is four and corresponds to the number of the scrapers. The magnetic rollers are located in the apparatus barrel, and each includes an outer layer and an inner core. The outer layer is sleeved onto the inner core. The inner core has a magnetic region and a non-magnetic region. The outer layers of the magnetic rollers are driven and connected through a gear. The outer layer of one of the magnetic rollers is connected with the motor and driven by the motor. Each scraper corresponds to the outer layer of a corresponding one of the magnetic rollers. When the iron filings adsorbed on the outer layer are rotated to the non-magnetic region, the iron filings can be scraped off by the scrapers.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 30, 2019
    Inventor: Jian Guo CHEN
  • Patent number: 10102984
    Abstract: The disclosed concept relates generally to current sense techniques and apparatus for arc fault and ground fault receptacles, e.g., circuit interrupters, and, more particularly, to arc fault and ground fault receptacles including a shunt stationary terminal exhibiting both mechanical and electrical functionality. The shunt stationary terminal is composed of a steel or steel alloy and copper or copper alloy composite having a current shunt integrated therein.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 16, 2018
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Saivaraprasad Murahari, Jian Guo Chen, Hongzhi Zhou
  • Publication number: 20180033569
    Abstract: The disclosed concept relates generally to current sense techniques and apparatus for arc fault and ground fault receptacles, e.g., circuit interrupters, and, more particularly, to arc fault and ground fault receptacles including a shunt stationary terminal exhibiting both mechanical and electrical functionality. The shunt stationary terminal is composed of a steel or steel alloy and copper or copper alloy composite having a current shunt integrated therein.
    Type: Application
    Filed: July 28, 2016
    Publication date: February 1, 2018
    Applicant: EATON CORPORATON
    Inventors: SAIVARAPRASAD MURAHARI, JIAN GUO CHEN, HONGZHI ZHOU
  • Patent number: 9778902
    Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Chengzhou Li, Albert Molina, Joseph H. Othmer, Steven C. Pinault, Meng-Lin Yu, Joseph Williams, Ramon Sanchez Perez, Jian-Guo Chen
  • Patent number: 9362977
    Abstract: In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes non-overlapping chunks of incoming antenna data, where each chunk is smaller than the preamble length, to detect the signature of the transmitted preamble. For each chunk processed, chips of the chunk are correlated with possible signatures employed by the wireless network to update a set of correlation profiles, each profile comprising a plurality of profile values. Further, an intermediate detection is performed by comparing the updated profile values to an intermediate threshold that is also updated for each chunk. Upon receiving the final chunk, the correlation profiles are updated, and a final preamble detection is made by comparing the updated profile values to a final threshold. Detections are performed on an incremental basis to meet latency requirements of the wireless network.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Patent number: 9223752
    Abstract: A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 9207910
    Abstract: A digital signal processor is provided having an instruction set with an xK function that uses a reduced look-up table. The disclosed digital signal processor evaluates an xK function for an input value, x, by computing Log(x) in hardware; multiplying the Log(x) value by K; and determining the xK function by applying an exponential function in hardware to a result of the multiplying step. One or more of the computation of Log(x) and the exponential function employ at least one look-up table having entries with a fewer number of bits than a number of bits in the input value, x.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 9184787
    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Meng-Lin Yu, Jian-Guo Chen, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko
  • Patent number: 9176735
    Abstract: Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 9170776
    Abstract: A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 9128790
    Abstract: A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: September 8, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 9069685
    Abstract: A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values for the non-linear function that are near the value, x, from at least one look-up table, wherein the at least one look-up table stores a subset of values for the non-linear function; and interpolating the two or more obtained values to obtain a result, y. The interpolation may comprise, for example, a linear interpolation or a polynomial interpolation. In a further variation, a modulo arithmetic operation can be employed for a periodic non-linear function.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 9069686
    Abstract: A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size and exponentially varying step-sizes. A digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for the non-linear function that are near the value, x, wherein the at least one look-up table stores a subset of values for the non-linear function using exponentially-varying step sizes; and interpolating the at least two obtained values to obtain a result, y. A position of a leading zero in the value, x, can be used as an index into the at least one look-up table. The interpolation can comprise, for example, a linear interpolation or a polynomial interpolation. A modulo arithmetic operation can optionally be employed for a periodic non-linear function.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Jian-Guo Chen, Samer Hijazi, Joseph Williams
  • Patent number: 8804672
    Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: August 12, 2014
    Assignee: LSI Corporation
    Inventors: Ivan L. Mazurenko, Alexander A. Petyushko, Meng-Lin Yu, Jian-Guo Chen
  • Publication number: 20140086356
    Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
    Type: Application
    Filed: October 26, 2012
    Publication date: March 27, 2014
    Applicant: LSI Corporation
    Inventors: Kameran Azadet, Chengzhou Li, Albert Molina, Joseph H. Othmer, Steven C. Pinault, Meng-Lin Yu, Joseph Willimas, Ramon Sanchez Perez, Jian-Guo Chen
  • Publication number: 20140064338
    Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 6, 2014
    Applicant: LSI Corporation
    Inventors: Meng-Lin Yu, Jian-Guo Chen, Alexander Alexandrovich Petyushko, Ivan Leonidovich Mazurenko