Abstract: A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited strict priority and smooth deficit weighted round robin for all user classes. The network operator selects one of the four schemes by enabling or disabling certain bits in the hardware device.

Abstract: A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.

Abstract: A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.

Abstract: A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited strict priority and smooth deficit weighted round robin for all user classes. The network operator selects one of the four schemes by enabling or disabling certain bits in the hardware device.

Abstract: An aqueous microemulsion polymerization procedure is described in which very small colloidal polymer particles are produced from tetrafluoroethylene monomer. The polymerization procedure involves adding a free-radical initiator to a mixture of a microemulsion of at least one liquid saturated organic compound; and tetrafluoroalkyl ethylene.

Abstract: An aqueous microemulsion polymerization procedure is described in which very small colloidal melt-processible fluoropolymer particles are produced from at least one monomer and optionally TFE. The polymerization procedure involves initiating polymerization by adding a free-radical initiator to a microemulsion of at least one liquid organic compound and at least one free-radical polymerizable monomer to the microemulsion.

Abstract: An aqueous microemulsion polymerization procedure is described in which very small colloidal polymer particles are produced from tetrafluoroethylene monomer. The polymerization procedure involves adding a free-radical initiator to a mixture of a microemulsion of at least one liquid saturated organic compound; and tetrafluoroalkyl ethylene.