Patents by Inventor Jian Liang

Jian Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12155305
    Abstract: A boost converter that provides a wide average current limiting range includes a switch coupled to an inductor output and a power input, a diode coupled to the inductor output and an output terminal load and configured to conduct current in only one direction away from the inductor output and toward the output terminal, a clamp circuit coupled to the diode and the switch, and a minimum time off module coupled to the diode and the switch. The clamp circuit is configured to clamp an inductor output current to a reference current while the converter is operating in a continuous conduction mode (CCM) of operation. The minimum time off module is configured to cause the inductor output current to be zero for at least a time Toff while the converter is operating in a pulse frequency modulation (PFM) mode of operation.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: November 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jian Liang, Chen Feng, Zichen Feng
  • Patent number: 12151493
    Abstract: An auxiliary tool includes a first stamping plate, a guiding frame, and a magnetic element. The first stamping plate is detachably attached on a first side wall of a container, and has a plurality of positioning grooves indently and spacedly formed on a first outer surface of the first stamping plate. The guiding frame has an engagement rim detachably engaging with one of the positioning grooves, and a supporting platform shaped and sized to correspond to the stamp. The magnetic element is mounted on the guiding frame to provide a magnetic attractive force for magnetically attracting the stamp so that a user is able to impart an impact on the stamp for forming a printed text on a workpiece.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: November 26, 2024
    Inventor: Jian Liang
  • Publication number: 20240370967
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Kalyan Kumar BHIRAVABHATLA, Andrew Evan GRUBER, Rahul Sunil KUKREJA, Vishwanath Shashikant NIKAM, Tao WANG, Jian LIANG
  • Publication number: 20240365949
    Abstract: An instant self-cleaning hair comb includes a lower shell and an upper shell. A spring and a push button are sequentially arranged between the lower shell and the upper shell, and a comb and a push plate are sequentially arranged outside the lower shell and the upper shell. The comb is configured to comb out the hair. The push plate is configured to push out the hair twined on the comb. The lower shell is configured to fix the comb and compress the spring. The spring is configured to be connected with the push button and the lower shell. The push button is configured to adjust the spring and the lower shell. The upper shell is configured to be connected with the lower shell and fix the push button and the spring. The efficiency of cleaning the hair comb is increased to shorten the cleaning time.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 7, 2024
    Inventor: JIAN LIANG
  • Publication number: 20240357078
    Abstract: A method of encoding or decoding video data includes determining, for a current block, a plurality of blocks for fusing; determining a respective first weight for two or more pixels of a first block of the plurality of blocks based on a respective position of the two or more pixels of the first block; determining a respective second weight for two or more pixels of a second block of the plurality of blocks; fusing the two or more pixels of the first block and the two or more pixels of the second block based on the respective first weight for the two or more pixels of the first block and the respective second weight for the two or more pixels of the second block to generate a prediction signal; and encoding or decoding the current block based on the prediction signal.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 24, 2024
    Inventors: Jian-Liang Lin, Po-Han Lin, Vadim Seregin, Marta Karczewicz, Yao-Jen Chang, Zhi Zhang
  • Publication number: 20240357079
    Abstract: A method of encoding or decoding video data includes selecting a group of blocks based on probing samples determined from pixels that are proximate to the blocks in the group of blocks and current probing samples determined from pixels that are proximate to a current block; fusing the blocks in the group of blocks to generate a prediction signal; and encoding or decoding the current block based on the prediction signal.
    Type: Application
    Filed: April 11, 2024
    Publication date: October 24, 2024
    Inventors: Jian-Liang Lin, Po-Han Lin, Vadim Seregin, Marta Karczewicz, Yao-Jen Chang, Zhi Zhang
  • Publication number: 20240333911
    Abstract: A method of encoding or decoding video data, the method comprising: applying a sub-pel precision mode to generate a prediction block for a current block of the video data, wherein a syntax element indicates that the sub-pel precision mode is applied to the current block and applying the sub-pel precision mode comprises: applying an interpolation filter to samples of a reference region to generate an array of samples at full-pel and sub-pel precision; and identifying, within the array, a reference template of the prediction block, wherein the reference template of the prediction block is a best match for a template of the current block within the array, wherein a template pattern defines a shape of the reference template of the prediction block and the template of the current block; and encoding or decoding the current block using the prediction block for the current block.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 3, 2024
    Inventors: Po-Han Lin, Jian-Liang Lin, Vadim Seregin, Marta Karczewicz
  • Publication number: 20240323592
    Abstract: The present disclosure provides an acoustic output device including an acoustic driver, and a first cavity and a second cavity acoustically coupled to the acoustic driver. The first cavity and the second cavity are provided with a first acoustic hole and a second acoustic hole, respectively, from which the acoustic driver radiate sounds with a phase difference to an outside environment. Within a target frequency band, a near-field sound radiated from the first acoustic hole and a near-field sound radiated from the second acoustic hole may have a near-field sound pressure level difference of less than 6 dB, and the sound radiated by the acoustic output device to a far-field has directivity, which is manifested in that the sounds radiated from the two acoustic holes have a far-field sound pressure level difference of not less than 3 dB in at least one pair of opposite directions.
    Type: Application
    Filed: October 31, 2023
    Publication date: September 26, 2024
    Applicant: SHENZHEN SHOKZ CO., LTD.
    Inventors: Zhen WANG, Jianing LIANG, Lei ZHANG, Xin QI
  • Publication number: 20240311207
    Abstract: Aspects of the disclosure are directed to coordination. In accordance with one aspect, an apparatus including a plurality of slices, wherein each slice of the plurality of slices is configured for distributed information processing; and a plurality of dedicated databuses, wherein each slice of the plurality of slices is coupled to one of the plurality of dedicated databuses and each slice of the plurality of slices is configured for local coordination for the distributed information processing.
    Type: Application
    Filed: March 15, 2023
    Publication date: September 19, 2024
    Inventors: Jian LIANG, Hu YI, Tao WANG, Fei XU, Ruobai FENG
  • Publication number: 20240297981
    Abstract: A method of encoding or decoding video data includes constructing a template matching candidate list for a current block of the video data based on a plurality of template patterns; and encoding or decoding the current block based on the template matching candidate list.
    Type: Application
    Filed: February 15, 2024
    Publication date: September 5, 2024
    Inventors: Po-Han Lin, Jian-Liang Lin, Bappaditya Ray, Yao-Jen Chang, Han Huang, Vadim Seregin, Marta Karczewicz
  • Patent number: 12079897
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: September 3, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Kalyan Kumar Bhiravabhatla, Andrew Evan Gruber, Rahul Sunil Kukreja, Vishwanath Shashikant Nikam, Tao Wang, Jian Liang
  • Publication number: 20240283285
    Abstract: A power system includes a transistor device (e.g., one or more NFETs) is coupled between input voltage and switching node terminals, to provide a variable sense resistance. The system may further include low-side and high-side switching elements, with the low-side switching element coupled between a ground terminal and the switching node terminal, and the high-side switching element coupled between the switching node terminal and an output voltage terminal. The system may be configured to determine its mode of operation, based on primary and backup battery voltages, and enable a corresponding control loop based on that determined mode. With a control loop enabled, the system may be further configured to control the transistor device to provide a variable sense resistor based on a given control parameter. The low-side switching element may be shared by the modes, and external to a chip that includes the high-side switching element and transistor device.
    Type: Application
    Filed: February 20, 2023
    Publication date: August 22, 2024
    Inventors: Jing Ji, Jian Liang, Shih-chao Hsu, Zejing Wang
  • Publication number: 20240265486
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for backface culling for guard band clipping primitives. A graphics processor may identify at least one backface primitive in a set of primitives that extends beyond at least one guard band, where the at least one backface primitive is identified based on a set of fixed point coordinates. The graphics processor may cull the at least one backface primitive. The graphics processor may transmit an indication of the culled at least one backface primitive.
    Type: Application
    Filed: February 2, 2023
    Publication date: August 8, 2024
    Inventors: Tao WANG, Ashokanand NEELAMBARAN, Jian LIANG, Xiayang ZHAO, Lingjun CHEN
  • Patent number: 12050005
    Abstract: A convenient and easy-to-use LED luminaire capable of adjusting the illumination angle of a light source in a combined manner is provided. The luminaire includes a cover, an upper shell, a lens, a PCB, a battery holder, an iron sheet, a lower shell, a base shell, a magnet, a base cover plate, a detection module, and a control platform. Through the combination of multiple groups of lights and multiple groups of lenses at different angles, the illumination angle of the luminaire can be conveniently changed to concentrate light on a specific area. The control platform adopting a cloud platform remotely controls the luminaire. A brightness adjustment system adopts a brightness estimation model to automatically adjust the brightness of the luminaire. A voice conversion submodule adopts a language model to extract command voice of a user into instruction information.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: July 30, 2024
    Assignees: Shen Zhen QianHai Dreamlink Technology Co., Ltd, Daoxian Jingwei Electronics Co., Ltd
    Inventors: Yong Ma, Jian Liang
  • Publication number: 20240223081
    Abstract: Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN<VOUT), the comparator circuit disables the control circuit and enables the driver circuit, which in turn fully turns on a high-side switching element during high-side on-phase. In contrast, during start-up operation or an output short-to-ground condition (VIN?VOUT), the comparator circuit disables the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side switching element, so the current through the switching element is regulated, and the switching node voltage is regulated to about a threshold voltage higher than VIN. In this manner, the comparator circuit controls the driver circuit and the control circuit, which in turn allow the boost converter to operate in a normal fashion even when VIN is higher than VOUT.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 4, 2024
    Inventor: Jian Liang
  • Publication number: 20240223748
    Abstract: A method of coding video data comprises: determining a template pattern from among a set of two or more template patterns; identifying a reference template based on a similarity of the reference template and a current template, wherein the reference template and the current template have a shape defined by the template pattern, the reference template includes previously reconstructed samples and the current template includes reference samples of a current block of a current picture of the video data; obtaining, based on the reference template, a prediction block for a current block of a current picture of the video data; and encoding or decoding the current block based on the prediction block.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 4, 2024
    Inventors: Po-Han Lin, Jian-Liang Lin, Vadim Seregin, Marta Karczewicz
  • Publication number: 20240221279
    Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a sliced low-resolution Z buffer (LRZ) that is communicatively coupled to each hardware slice of the plurality of hardware slices, and that comprises a plurality of LRZ regions. Each hardware slice is configured to store, in an LRZ region corresponding exclusively to the hardware slice among the plurality of LRZ regions, a pixel tile assigned to the hardware slice.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventors: Xuefeng Tang, Jian Liang, Tao Wang, Dong Zhou
  • Patent number: 12019718
    Abstract: An identity authentication method is provided, including: acquiring a raw feature of a user; calling an identity authentication model to extract a primary attribute feature vector in the raw feature, the primary attribute feature vector being an unbiased feature representation for selectively decoupling m?1 domain discrepancy features in the raw feature, and m being an integer greater than 2; and performing unbiased identity authentication based on the primary attribute feature vector to obtain an identity authentication result.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 25, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Jian Liang, Yuren Cao, Chenbin Zhang, Kun Bai
  • Publication number: 20240154529
    Abstract: A boost converter control method includes: receiving an output voltage; receiving an output voltage target; triggering a snooze phase start of an inactive load mode based on a comparison of the output voltage relative to the output voltage target plus a first output voltage target offset; and triggering a snooze phase end of the inactive load mode based on a comparison of the output voltage relative to the output voltage target plus a second output voltage target offset, the second output voltage target offset greater than the first output voltage target offset.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 9, 2024
    Inventors: Chen FENG, Jian LIANG, Guangxu WANG
  • Publication number: 20240146183
    Abstract: In some examples, an apparatus includes a filter, a voltage-to-current conversion circuit, a first current source, a second current source, a capacitor, a comparator, and a buffer. The filter has a first input voltage (VIN) input and a filter output. The voltage-to-current conversion circuit has a first input, a second VIN input, and a current output, the first input coupled to the filter output. The first current source is coupled between the current output and ground terminal. The second current source is coupled between a power terminal and the current output. The capacitor is coupled between the current output and ground terminal. The comparator has a comparator output, a comparator input, and a reference voltage (Vref) input, the comparator input coupled to the current output. The buffer has a buffer input and a buffer output, the buffer input coupled to the comparator output.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Inventors: Jing JI, Jian LIANG