Patents by Inventor Jian-Ming Wang

Jian-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10826246
    Abstract: An electrical connector includes an insulative housing and a plurality of contacts retained within the housing as a contact module. The housing includes a base and a mating tongue forwardly extending from the base. The contacts are arranged with two rows contacting sections respectively exposed upon two opposite surfaces of the mating tongue, and one row mounting sections for mounting to a same plane of a printed circuit board. Each contact has a linking section between the contacting section and the mounting section. The contacts are grouped by one grounding contact associated with a pair of neighboring differential pair signal contacts in an isosceles triangular configuration wherein the grounding contact is located at the top apex. The linking section of grounding contact of the outermost group is widened compared with those of the remaining contacts for lowering the corresponding impedance.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 3, 2020
    Assignees: FU DING PRECISION INDUSTRIAL (ZHENGZHOU) CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Wei-Liang Zhang, Jian-Long Hu, Xiang-Dong Wang, Dao-Zhen Bian, Wen-Ming Wu
  • Publication number: 20200059044
    Abstract: An electrical connector includes an insulative housing and a plurality of contacts retained within the housing as a contact module. The housing includes a base and a mating tongue forwardly extending from the base. The contacts are arranged with two rows contacting sections respectively exposed upon two opposite surfaces of the mating tongue, and one row mounting sections for mounting to a same plane of a printed circuit board. Each contact has a linking section between the contacting section and the mounting section. The contacts are grouped by one grounding contact associated with a pair of neighboring differential pair signal contacts in an isosceles triangular configuration wherein the grounding contact is located at the top apex. The linking section of grounding contact of the outermost group is widened compared with those of the remaining contacts for lowering the corresponding impedance.
    Type: Application
    Filed: August 19, 2019
    Publication date: February 20, 2020
    Inventors: WEI-LIANG ZHANG, JIAN-LONG HU, XIANG-DONG WANG, DAO-ZHEN BIAN, WEN-MING WU
  • Patent number: 10516341
    Abstract: Synchronous rectifier gate voltage boost method and system. At least some of the example embodiments are methods of operating a power converter to create an output voltage, including storing energy in a field of a main transformer arranged for flyback operation, the storing during periods of time when a primary switch is conductive and current flows through a primary winding of the transformer; and then transferring energy from the field of the main transformer to the output voltage on a secondary side of the power converter; activating a secondary rectifier (SR) switch on the secondary side of the power converter during periods of time when the primary switch is non-conductive, the activating by: driving a gate of the SR switch without boost if the output voltage is above a first threshold; and driving the gate of the SR switch with boost if the output voltage is below the first threshold.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 24, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jian Ming Fu, Chou-Sheng Wang, Zhibo Tao
  • Patent number: 10051733
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: August 14, 2018
    Assignee: SanDisk Technologies Inc.
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
  • Patent number: 9230919
    Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: January 5, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
  • Patent number: 9209159
    Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: December 8, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
  • Publication number: 20150223335
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Application
    Filed: April 13, 2015
    Publication date: August 6, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
  • Patent number: 9006912
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: April 14, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
  • Publication number: 20150054177
    Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
  • Patent number: 8878368
    Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: November 4, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
  • Publication number: 20130299959
    Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheeman Yu, Hem Takiar
  • Patent number: 8487441
    Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: July 16, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheemen Yu, Hem Takiar
  • Patent number: 8461675
    Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: June 11, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Ken Jian Ming Wang, Chih-Chin Liao, Han-Shiao Chen
  • Publication number: 20120273968
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
  • Patent number: 8269321
    Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: September 18, 2012
    Assignee: Broadcom Corporation
    Inventors: Ken Jian Ming Wang, Matthew Vernon Kaufmann
  • Patent number: 8269323
    Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: September 18, 2012
    Assignee: Broadcom Corporation
    Inventors: Rezaur Rahman Khan, Ken Jian Ming Wang
  • Publication number: 20120187545
    Abstract: Methods, systems, and apparatuses are described for improved integrated circuit packages. An integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing one or both surfaces of the semiconductor substrate. The die is mounted to the first surface of the semiconductor substrate. An encapsulating material encapsulates the die on the first surface of the semiconductor substrate.
    Type: Application
    Filed: June 30, 2011
    Publication date: July 26, 2012
    Applicant: BROADCOM CORPORATION
    Inventors: Rezaur Rahman Khan, Edward Law, Ken Jian Ming Wang
  • Patent number: 8217522
    Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 10, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
  • Publication number: 20120164828
    Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.
    Type: Application
    Filed: March 2, 2012
    Publication date: June 28, 2012
    Inventors: Hem Takiar, Cheeman Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
  • Patent number: 8193613
    Abstract: According to one embodiment, a semiconductor die having increased usable area has at least six sides. The semiconductor die has a reduced stress at each corner of the die, resulting in smaller keep out zones near the corners of the semiconductor die, which allow the placement of bond pads near each corner of the die. The semiconductor die further allows the placement of active circuitry near each corner of the semiconductor die. One embodiment results in a 5.0% increase in usable area on the semiconductor die.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: June 5, 2012
    Assignee: Broadcom Corporation
    Inventors: Ken Jian Ming Wang, Ming Wang Sze