Patents by Inventor Jian-Ming Wang
Jian-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100252315Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: ApplicationFiled: June 21, 2010Publication date: October 7, 2010Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheeman Yu, Hem Takiar
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Patent number: 7806731Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.Type: GrantFiled: December 29, 2005Date of Patent: October 5, 2010Assignee: SanDisk CorporationInventors: Hem Takiar, Cheemen Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
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Patent number: 7746661Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: GrantFiled: June 8, 2006Date of Patent: June 29, 2010Assignee: SanDisk CorporationInventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
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Publication number: 20100019360Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.Type: ApplicationFiled: September 11, 2009Publication date: January 28, 2010Applicant: BROADCOM CORPORATIONInventors: Rezaur Rahman Khan, Ken Jian Ming Wang
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Patent number: 7618849Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.Type: GrantFiled: October 22, 2007Date of Patent: November 17, 2009Assignee: Broadcom CorporationInventors: Rezaur Rahman Khan, Ken Jian Ming Wang
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Publication number: 20090263969Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Inventors: Hem Takiar, Cheemen Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
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Patent number: 7592699Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.Type: GrantFiled: December 29, 2005Date of Patent: September 22, 2009Assignee: SanDisk CorporationInventors: Hem Takiar, Cheemen Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Han-Shiao Chen, Chih-Chin Liao
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Publication number: 20090194872Abstract: Methods, systems, and apparatuses for integrated circuit packages, transport containers, and for transporting integrated circuit packages are provided. A transport container for an integrated circuit package includes a body and a plurality of mounting features. The body has a surface that includes a package receiving region. The plurality of mounting features is positioned in the package receiving region. A first mounting feature is positioned on a first inner surface of the package receiving region and a second mounting feature is positioned on a second inner surface of the package receiving region. The package receiving region is configured to receive an integrated circuit package such that the received package is supported by the plurality of mounting features. The first and second mounting features coincide with respective spaces in first and second edges of an array of solder balls on a surface of the package.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Applicant: BROADCOM CORPORATIONInventors: Ken Jian Ming Wang, Edward Law
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Patent number: 7538438Abstract: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package. The dummy circuit pattern includes a plurality of straight line segments and a plurality of interrupt patterns to breakup one or more of the straight line segments. The interrupt patterns are provided so as to not electrically isolate areas of the dummy pattern, thus providing electrical continuity across the dummy circuit pattern.Type: GrantFiled: June 30, 2005Date of Patent: May 26, 2009Assignee: SanDisk CorporationInventors: Cheemen Yu, Ken Jian Ming Wang, Chin-Tien Chiu, Chih-Chin Liao, Han-Shiao Chen
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Publication number: 20090108473Abstract: Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in the first surface of the metal layer adjacent to the die-attach region. The adhesive material attaches a first surface of the die to the die-attach region and at least partially fills the recessed region(s). Excess adhesive material flows into the recessed region(s) during application of the die to the die-attach region, so that the side surfaces of the die remain substantially uncovered by the adhesive material. By preventing the excess adhesive material from covering the side surfaces of the die, the adhesive material is prevented from penetrating the side surfaces of the die, which could damage the die.Type: ApplicationFiled: October 26, 2007Publication date: April 30, 2009Applicant: BROADCOM CORPORATIONInventors: Ken Jian Ming Wang, Muh-Ren Lin, Rezaur Rahman Khan
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Publication number: 20090102030Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.Type: ApplicationFiled: October 22, 2007Publication date: April 23, 2009Applicant: BROADCOM CORPORATIONInventors: Rezaur Rahman Khan, Ken Jian Ming Wang
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Publication number: 20090057858Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.Type: ApplicationFiled: August 28, 2007Publication date: March 5, 2009Applicant: BROADCOM CORPORATIONInventors: Ken Jian Ming Wang, Matthew Vernon Kaufmann
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Publication number: 20080220206Abstract: According to one embodiment, a semiconductor die for increasing usable area of a wafer and for increasing yield has a substantially hexagonal shape. The wafer can have, for example, a circular shape. The semiconductor die can be diced by, for example, using a water-jet-guided laser. In one embodiment, the semiconductor die results in an approximately 2.0% to 4.0% reduction in the unusable area of the wafer. Moreover, the substantially hexagonal shape of the semiconductor die reduces stress at corners of the semiconductor die, thus increasing the yield of the wafer.Type: ApplicationFiled: March 6, 2007Publication date: September 11, 2008Inventors: Ken Jian Ming Wang, Ming Wang Sze
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Publication number: 20080220220Abstract: According to one embodiment, a semiconductor die having increased usable area has at least six sides. The semiconductor die has a reduced stress at each corner of the die, resulting in smaller keep out zones near the corners of the semiconductor die, which allow the placement of bond pads near each corner of the die. The semiconductor die further allows the placement of active circuitry near each corner of the semiconductor die. One embodiment results in a 5.0% increase in usable area on the semiconductor die.Type: ApplicationFiled: March 6, 2007Publication date: September 11, 2008Inventors: Ken Jian Ming Wang, Ming Wang Sze
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Patent number: 7355283Abstract: A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.Type: GrantFiled: April 14, 2005Date of Patent: April 8, 2008Assignee: SanDisk CorporationInventors: Chin-Tien Chiu, Chih-Chin Liao, Ken Jian Ming Wang, Han-Shiao Chen, Cheemen Yu, Hem Takiar
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Publication number: 20070284727Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.Type: ApplicationFiled: June 8, 2006Publication date: December 13, 2007Inventors: Chih-Chin Liao, Han-Shiao Chen, Chin-Tien Chiu, Ken Jian Ming Wang, Cheemen Yu, Hem Takiar
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Patent number: 7068934Abstract: An optical interconnect comprises an input configured to receive light of a plurality of light wavelengths and a plurality of holographic optical elements. Each element configured to reflect one out of the plurality of light wavelengths and allowing others of the plurality of wavelengths to not be reflected. Each of a plurality of prisms is configured to rotate received light at a different angle than any of the other prisms. For each holographic optical element, one of the plurality of prisms is positioned to receive and rotate light reflected by that holographic element. Each of a plurality of beam splitters is positioned to receive light rotated by a respective one of the plurality of prisms and all the plurality of beam splitters direct light to an output of the optical interconnect.Type: GrantFiled: March 17, 2004Date of Patent: June 27, 2006Assignee: InterDigital-Technology CorporationInventors: Emmanuel Kanterakis, Jian-Ming Wang
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Publication number: 20060101331Abstract: A method for automated test-case generation. A first type SDL is translated to a second type SDL in accordance with translation rules. The second type SDL is analyzed using a coverage analysis algorithm for calculating the coverage of the second type SDL, and test cases corresponding to the second type SDL are generated according to the coverage. Test cases complying with tree and tabular combined notation (TTCN) formats are generated according to a tree structure corresponding to the second type SDL and TTCNs.Type: ApplicationFiled: January 13, 2005Publication date: May 11, 2006Inventors: Farn Wang, Jian-Ming Wang, An-Yi Chen, Chiu-Han Hsiao
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Publication number: 20040175190Abstract: An optical interconnect comprises an input configured to receive light of a plurality of light wavelengths and a plurality of holographic optical elements. Each element configured to reflect one out of the plurality of light wavelengths and allowing others of the plurality of wavelengths to not be reflected. Each of a plurality of prisms is configured to rotate received light at a different angle than any of the other prisms. For each holographic optical element, one of the plurality of prisms is positioned to receive and rotate light reflected by that holographic element. Each of a plurality of beam splitters is positioned to receive light rotated by a respective one of the plurality of prisms and all the plurality of beam splitters direct light to an output of the optical interconnect.Type: ApplicationFiled: March 17, 2004Publication date: September 9, 2004Applicant: InterDigital Technology CorporationInventors: Emmanuel Kanterakis, Jian-Ming Wang
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Patent number: 6711358Abstract: An optical apparatus comprises a phase grating, an input-ring array, an output-ring array and an optical interconnect. The phase grating produces a modulated light beam for each of a plurality of processing elements. The modulated light beams have a plurality of light wavelengths. An input-ring array receives the plurality of data modulated light beams. An output-ring array outputs a light beam to each processing element. An optical interconnect transfers light from the input-ring array to the output ring array and uniquely rotates each wavelength of the transferred light.Type: GrantFiled: March 5, 2003Date of Patent: March 23, 2004Assignee: InterDigital Technology CorporationInventors: Emmanuel Kanterakis, Jian-Ming Wang