Abstract: This disclosure relates to a seal for a power module and an electric energy conversion and transmission device. The seal for the power module comprising a housing having a first side surface and a second side surface opposite to each other and pins sticking out of the first side surface, the seal comprises a peripheral wall extending continuously in the circumferential direction to define a accommodating space, which is adaptable for accommodating the power module, the peripheral wall is elastic and has a first end and a second end opposite to each other, and the peripheral wall is configured such that when the power module is completely accommodated in the accommodating space, the first end of the peripheral wall is at least higher than the first side surface of the housing.

Abstract: A floating-point computing-in-memory device, an exponent computing memory module and a mantissa computing memory module are provided. The floating-point computing-in-memory device includes the exponent computing memory module and the mantissa computing memory module. The exponent computing memory module includes a plurality of weighting exponent memory circuits, a plurality of exponent computing circuits and a comparison circuit. The exponent computing circuits are used to obtain a plurality of exponent products. The mantissa computing memory module includes a bit shifting circuit, a plurality of weighting mantissa memory circuits, a plurality of mantissa computing circuits, a shift-and-addition circuit, a plurality of weighting sign memory circuits, a plurality of sign computing circuits and an addition circuit. The mantissa computing circuits and the shift-and-addition circuit are used to obtain a plurality of mantissa products. The sign computing circuits are used to obtain a plurality of sign products.

Abstract: A package includes a semiconductor carrier, a first die, a second die, and an electron transmission path. The first die is disposed over the semiconductor carrier and is located at a first tier. The second die is stacked on the first die and is located at a second tier. The electron transmission path extends vertically and is electrically connected to a ground volage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is located at the first tier, and a third portion of the electron transmission path is located at the second tier.

Abstract: A machine learning-based synthesis runtime prediction method includes collecting initial training data from a database, selecting featured training data from the initial training data useful for predicting runtimes, building a machine learning model for predicting the runtimes based on the featured training data, measuring a loss and an accuracy of the machine learning model, performing standardization and/or normalization on the featured training data of the training data to generate updated training data if the loss and/or the accuracy fails to meet predefined criteria, performing clustering at least once on the updated training data to generate clustered training data, identifying at least one outlier from the clustered training data, removing the at least one outlier to generate filtered training data, and preprocessing, training and testing the machine learning model based on the filtered training data until the loss and the accuracy meet the predefined criteria.

Abstract: A method includes attaching a first die and a second die to a first wafer, the first wafer comprising: a first carrier substrate; and a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers; attaching a third die to the first die and a fourth die to the second die; attaching a second wafer to the third die and the fourth die, the second wafer comprising: a second carrier substrate; and a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers; removing the first carrier substrate; patterning the first dielectric layers to expose conductive features of the first die and the second die; and forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.

Abstract: A vacuum system has a condenser and a root vacuum pump set, wherein the condenser is an independent inlet condenser set connected to a generator including an air cooling power generator condenser. A pressure sensor is installed on the independent inlet condenser set for detecting a first input pressure. Air outputted from the independent inlet condenser set is compressed by the root vacuum pump set. A backing pump receives an air outputted from the root vacuum pump set through an output pipe. A bypass pipe is connected between an output end of the root vacuum pump set and a vapor-liquid separator connected to the backing pump. A central controller serves to receive the first input pressure and determine to control the air from the root vacuum pump set to be outputted to the output pipe or the bypass pipe by a control valve.

Abstract: A method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.

Abstract: In one example, a method includes method comprising: receiving audio data generated by a microphone of a current computing device; identifying, based on the audio data, one or more computing devices that each emitted a respective audio signal in response to speech reception being activated at the current computing device; and selecting either the current computing device or a particular computing device from the identified one or more computing devices to satisfy a spoken utterance determined based on the audio data.

Abstract: A packaging module and a manufacturing method therefor are provided. The packaging module includes a first packaging structure and a magnetic component. The first packaging structure includes a plastic packaging structure for encapsulating a non-magnetic component and metal connecting structures and exposing top surfaces of the metal connecting structures. The magnetic component is disposed above the first packaging structure includes terminal bond pads and a metal plating layer disposed between the metal connecting structures and the terminal bond pads. Vertical projections of the metal connecting structures and the terminal bond pads partially overlap on the horizontal plane. The metal plating layer contacts with the metal connecting structures and the terminal bond pads to form an electrical connection. The packaging module can enhance the reliability of soldering, further reduce the current impedance of the inductance, and decrease the thermal resistance from the inductance to the module output ground.

Abstract: A facility for recovering carbon dioxide from a feed gas flow, including a unit for treating the feed gas flow in order to produce, from feed gas flow, a carbon dioxide-rich gas flow and a nitrogen-rich gas flow, a compression stage for compressing the feed gas flow, an expansion stage capable of outputting mechanical energy generated by the expansion of the nitrogen-rich gas flow, a thermal device arranged to enable heat transfers to take place between the gas flow leaving the compression stage and the nitrogen-rich gas flow prior to expansion, and a device for utilising the mechanical energy output by the expansion stage.

Abstract: A package includes a semiconductor carrier, a first die, a second die, a redistribution structure, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The redistribution structure is over the second die. The electron transmission path extends from the semiconductor carrier to the redistribution structure. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die, and a third portion of the electron transmission path is aside the second die.

Abstract: The present disclosure provides systems and methods for calibration-free instant motion tracking useful, for example, for rending virtual content in augmented reality settings. In particular, a computing system can iteratively augment image frames that depict a scene to insert virtual content at an anchor region within the scene, including situations in which the anchor region moves relative to the scene. To do so, the computing system can estimate, for each of a number of sequential image frames: a rotation of an image capture system that captures the image frames; and a translation of the anchor region relative to an image capture system, thereby providing sufficient information to determine where and at what orientation to render the virtual content within the image frame.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Abstract: An all-oxide transistor structure includes a substrate, a first transistor, a second transistor, a third transistor and a fourth transistor. The substrate has an upper surface. The first transistor is disposed on the upper surface of the substrate. The second transistor is disposed on the upper surface of the substrate, wherein the second transistor is electrically connected to the first transistor. The third transistor is electrically connected to the second transistor and overlapped with the second transistor in a first direction, wherein the first direction is parallel to a normal direction of the upper surface of the substrate. The fourth transistor is disposed on the upper surface of the substrate, wherein the fourth transistor is electrically connected to the first transistor, the second transistor and the third transistor.

Abstract: A transformer structure can include: a substrate encapsulating at least two windings that are isolated from each other, where each winding includes a coil body and lead-out terminals coupled to the coil body; and a magnetic encapsulation body encapsulating at least one side of the substrate, where the magnetic encapsulation body includes an insulating main material and magnetic particles dispersed in the insulating main material.

Abstract: A semiconductor device includes a first die, a second die and a third die. The first die has a first side including a plurality of first connecting structures and a second side including a plurality of second connecting structures, where the first side is opposite to the second side. The second die has a third side including a plurality of third connecting structures, where the plurality of third connecting structures are in contact with the plurality of first connecting structures of the first die. The third die has a fourth side including a plurality of fourth connecting structures, where the plurality of fourth connecting structures are in contact with the plurality of second connecting structures of the first die. A first pitch of the plurality of first connecting structures and a second pitch of the plurality of third connecting structures are less than a third pitch of the plurality of fourth connecting structures.

Abstract: The present disclosure is generally related to a data processing system to process data packets in a voice activated computer network environment. The data processing system can improve the efficiency of the network by generating non-video data responses to voice commands received from a client device if a display associated with a client device is in an OFF state. A digital assistant application executed on the client device can send to the data processing system client device configuration data, which includes the state of the display device, among status data of other components of the client device. The data processing system can receive a current volume of speakers associated with the client device, and set a volume level for the client device based on the current volume level and a minimum response volume level at the client device.

Abstract: A method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.

Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.