Abstract: A matrix multiplier and an operation method thereof are provided. The matrix multiplier includes a plurality of first input lines, a plurality of second input lines and a computing array. The computing array includes a plurality of multiplication accumulation (MAC) cells. A first MAC cell of the plurality of MAC cells is coupled to a first corresponding input line of the plurality of first input lines and a second corresponding input line of the plurality of second input lines to receive a first input value and a second input value to perform a multiplication accumulation operation. When at least one of the first input value and the second input value is a specified value, the multiplication accumulation operation of the first MAC cell is disabled.

Abstract: The present disclosure provides a matrix device and an operation method thereof. The matrix device includes a transpose circuit and a memory. The transpose circuit is configured to receive a first element string representing a native matrix from a matrix source, wherein all elements in the native matrix are arranged in the first element string in one of a “row-major manner” and a “column-major manner”. The transpose circuit transposes the first element string into a second element string, wherein the second element string is equivalent to an element string in which all elements of the native matrix are arranged in another one of the “row-major manner” and the “column-major manner”. The memory is coupled to the transpose circuit to receive the second element string.

Abstract: A matrix multiplier and an operation method thereof are provided. The matrix multiplier includes a plurality of first input lines, a plurality of second input lines and a computing array. The computing array includes a plurality of multiplication accumulation (MAC) cells. A first MAC cell of the plurality of MAC cells is coupled to a first corresponding input line of the plurality of first input lines and a second corresponding input line of the plurality of second input lines to receive a first input value and a second input value to perform a multiplication accumulation operation. When at least one of the first input value and the second input value is a specified value, the multiplication accumulation operation of the first MAC cell is disabled.

Abstract: A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes a plurality of unit circuits. Each of the unit circuits includes a multiplying-adding circuit, a first register, and a second register. A first input terminal and a second input terminal of the multiplying-adding circuit are respectively coupled to a corresponding first input line and a corresponding second input line. An input terminal and an output terminal of the first register are respectively coupled to an output terminal and a third input terminal of the multiplying-adding circuit. The second register is coupled to the first register to receive and temporarily store a multiplication accumulation result. Wherein, the second registers of the unit circuits output the multiplication accumulation results in a column direction in a first output mode, and output the multiplication accumulation results in a row direction in a second output mode.

Abstract: The present invention provides an integrated water-cooled air conditioning device, which comprises a cooling water tank device and an air conditioning system. The cooling water tank device includes a cooling water tank. A water tank region is disposed at the bottom of the cooling water tank for accommodating water. The air conditioning system includes a compressor, a condenser, a regulator, and an evaporator connected sequentially by a refrigerant piping. The condenser is formed by spirally bending the refrigerant piping to a spiral hollow tube in the water tank region. Thereby, the air conditioning system and the cooling-water circulation system can be connected integrally for miniaturization. The shortcomings of long heat dissipation loop, high pressure loss, and large size can be solved. Accordingly, the installation costs can be lowered, and the subsequent maintenance management can be convenient.

Abstract: A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes calculation circuits, a control circuit, a multiplication circuit, and a routing circuit. The calculation circuits produce multiply-accumulate values. The control circuit receives a plurality of first element values of a first matrix. The control circuit classifies the first element values into at least one classification value. The multiplication circuit multiplies the classification value by a second element value of a second matrix in a low power mode to obtain at least one product value. The routing circuit transmits each of the product values to at least one corresponding calculation circuit in the calculation circuits in the low power mode.

Abstract: A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes a plurality of unit circuits. Each of the unit circuits includes a multiplying-adding circuit, a first register, and a second register. A first input terminal and a second input terminal of the multiplying-adding circuit are respectively coupled to a corresponding first input line and a corresponding second input line. An input terminal and an output terminal of the first register are respectively coupled to an output terminal and a third input terminal of the multiplying-adding circuit. The second register is coupled to the first register to receive and temporarily store a multiplication accumulation result. Wherein, the second registers of the unit circuits output the multiplication accumulation results in a column direction in a first output mode, and output the multiplication accumulation results in a row direction in a second output mode.

Abstract: A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes calculation circuits, a control circuit, a multiplication circuit, and a routing circuit. The calculation circuits produce multiply-accumulate values. The control circuit receives a plurality of first element values of a first matrix. The control circuit classifies the first element values into at least one classification value. The multiplication circuit multiplies the classification value by a second element value of a second matrix in a low power mode to obtain at least one product value. The routing circuit transmits each of the product values to at least one corresponding calculation circuit in the calculation circuits in the low power mode.

Abstract: A hardware architecture and a processing method for an activation function in a neural network are provided. A look-up table, which is a corresponding relation among multiple input ranges and linear functions, is provided. A difference between an initial value and an end value of the input range of each linear function is an exponentiation of base-2. These linear functions form a piecewise linear function to approximate the activation function. At least one bit value of an input value is used as an index to query the look-up table to determine a corresponding linear function. The part of bits value of the input value is fed into the determined linear function to obtain an output value. Accordingly, a range comparison may be omitted, and the number of bits of a multiplier-accumulator may be reduced, so as to achieve the objectives of low costs and low power consumption.

Abstract: The present invention provides an integrated water-cooled air conditioning device, which comprises a cooling water tank device and an air conditioning system. The cooling water tank device includes a cooling water tank. A water tank region is disposed at the bottom of the cooling water tank for accommodating water. The air conditioning system includes a compressor, a condenser, a regulator, and an evaporator connected sequentially by a refrigerant piping. The condenser is formed by spirally bending the refrigerant piping to a spiral hollow tube in the water tank region. Thereby, the air conditioning system and the cooling-water circulation system can be connected integrally for miniaturization. The shortcomings of long heat dissipation loop, high pressure loss, and large size can be solved. Accordingly, the installation costs can be lowered, and the subsequent maintenance management can be convenient.

Abstract: The disclosure proposes a method of fixed-rate line-based embedded video compression and an image processing apparatus using the same method. The method includes at least the following steps. A current encoding frame is received. Pixels in a current encoding frame are grouped on a line-by-line basis, and the grouped pixels are packed into pixel segments. Complexity information of a current pixel segment is calculated according to the pixels therein and neighboring pixels thereof. The current pixel segment is respectively encoded in a differential pulse-coding modulation (DPCM) mode and a truncation mode to generate a DPCM bitstream and a truncated bitstream according to a quantization parameter (QP). Either the DPCM bitstream or the truncated bitstream is selected and outputted according to the complexity information. An amount of bits used by the current pixel segment is feedback to calculate a new QP corresponding to a next pixel segment to be processed.

Abstract: The disclosure proposes a method of fixed-rate line-based embedded video compression and an image processing apparatus using the same method. The method includes at least the following steps. A current encoding frame is received. Pixels in a current encoding frame are grouped on a line-by-line basis, and the grouped pixels are packed into pixel segments. Complexity information of a current pixel segment is calculated according to the pixels therein and neighboring pixels thereof. The current pixel segment is respectively encoded in a differential pulse-coding modulation (DPCM) mode and a truncation mode to generate a DPCM bitstream and a truncated bitstream according to a quantization parameter (QP). Either the DPCM bitstream or the truncated bitstream is selected and outputted according to the complexity information. An amount of bits used by the current pixel segment is feedback to calculate a new QP corresponding to a next pixel segment to be processed.

Abstract: The present invention relates to a software radio system and a decoding apparatus and method thereof. According to an embodiment of the present invention, there is provided a forward error correction decoding apparatus for a software radio system, including: a receiving module for receiving decoding tasks from a plurality of uplink channels; and a decoder matrix for executing the decoding tasks, wherein the decoder matrix is shared by the plurality of uplink channels. The decoding apparatus and method as well as the software radio system according to the embodiments of the present invention can be well adapted to the high computing capabilities, sufficient flexibility and scalability as required by base station systems for next-generation wireless communication systems.

Abstract: A base station apparatus, methods of receiving and sending data, and a computer readable article of manufacture. A computer implemented method includes the following for receiving and sending data: receiving the data by an RF header module; grouping data received; transferring the grouped data to a data processing apparatus; distributing the grouped data into an uplink sub-channel; merging the distributed data using at least one downlink sub-channel; transferring the merged data to a transceiving apparatus; degrouping the merged data; and sending the merged data by RF header module. A method of receiving data, a method of sending data, and computer readable non-transitory articles of manufacture are also provided.

Abstract: A wireless communication system base station, and a remote radio head (RRH) and a computer-implemented synchronization method for the wireless communication system base station. The RRH is communicably coupled to a baseband unit (BBU) of the wireless communication system base station through a network, and the BBU processes and transmits downlink data to the RRH. The RRH includes: a time-delay measurement unit for measuring a time-delay for the downlink data to arrive at the RRH from the BBU; and a time-delay notification unit for notifying from the RRH to the BBU of time-delay data on the time-delay measured by the time-delay measurement unit, wherein the time-delay data is used to advance the starting time for the BBU to process and transmit the downlink data by an amount of time obtained based on the time-delay data.

Abstract: A wireless communication system base station, and a remote radio head (RRH) and a computer-implemented synchronization method for the wireless communication system base station. The RRH is communicably coupled to a baseband unit (BBU) of the wireless communication system base station through a network, and the BBU processes and transmits downlink data to the RRH. The RRH includes: a time-delay measurement unit for measuring a time-delay for the downlink data to arrive at the RRH from the BBU; and a time-delay notification unit for notifying from the RRH to the BBU of time-delay data on the time-delay measured by the time-delay measurement unit, wherein the time-delay data is used to advance the starting time for the BBU to process and transmit the downlink data by an amount of time obtained based on the time-delay data.

Abstract: A wireless communication transceiver and a mode switch device thereof. The transceiver includes: a first band transmission path; a first band reception path; a second band transmission path; a second band reception path; a path switch and a control unit. In a dual band time division duplexing mode, the control unit controls the path switch so that the path switch connects a received radio frequency signal from an antenna to the first band reception path, and connects a transmitted radio frequency signal from the second band transmission path to the antenna in an odd cycle or an even cycle; and controls the path switch so that the path switch connects a received radio frequency signal from the antenna to the second band reception path, and connects a transmitted radio frequency signal from the first band transmission path to the antenna in another odd cycle or another even cycle.

Abstract: A slew rate control circuit is provided. The slew rate control circuit includes at least one switch and an inverter. A first end of the switch is coupled to a power terminal. A toggle end of the switch is coupled to a first control terminal. A second end of the switch is coupled to an output terminal. An output end of the inverter is coupled to the output terminal. An input end of the inverter is coupled to an input terminal. A voltage at the first control terminal conducts the switch to reduce the slew rate when a large voltage variation occurs at the output terminal. A method of controlling a slew rate and a slew rate control device are provided.

Abstract: A radioactive material containing chitosan for inhibiting cancer and a preparation method thereof are revealed. The adioactive material containing chitosan is formed by using SOCTA chelating agent to connect chitosan and radionuclides such as 188Re, and Tc-99m etc. The preparation method of the radioactive material containing chitosan includes the steps of: prepare SOCTA-Chitosan compound; and prepare M(radionuclide)-SOCTA-Chitosan compound. By biocompatibility and clotting in alkaline environment of human blood of chitosan, the radioactive material containing chitosan is injected into cancer and staying there for a long time so as to achieve effectively treatment.

Abstract: A wireless communication system base station, and a remote radio head (RRH) and a computer-implemented synchronization method for the wireless communication system base station. The RRH is communicably coupled to a baseband unit (BBU) of the wireless communication system base station through a network, and the BBU processes and transmits downlink data to the RRH. The RRH includes: a time-delay measurement unit for measuring a time-delay for the downlink data to arrive at the RRH from the BBU; and a time-delay notification unit for notifying from the RRH to the BBU of time-delay data on the time-delay measured by the time-delay measurement unit, wherein the time-delay data is used to advance the starting time for the BBU to process and transmit the downlink data by an amount of time obtained based on the time-delay data.