Abstract: A process of automatically translating an extended activity diagram (EAD) into a hardware component graph (HCG).

Abstract: A method to hardware component graph translation process for a high-level programming language, which analyzes codes of a high-level programming language to collect class information and store the collected class information in a class information object, and generates a temporal hardware component graph to obtain corresponding public methods, parameters, return values. The public methods, parameters, return values are linked to a class start node. A method call table is generated according to both one or more in/out edges of a method call node and method information of the class information object. The one or more edges linked to the method call node are changed to a method start node according to the method call table to accordingly represent a respective method call in the codes of the high-level programming language and translate the temporal hardware component graph into a hardware component graph allowable to correspond to hardware components.

Abstract: A method for testing a hardware circuit block written in a hardware description language (HDL) is provided, which can automatically produce a test pattern and an error message. The method includes converting an original class into a wrapper class, wherein the wrapper class, as compared to the original class, additionally records all input and output data of the hardware circuit block; producing a top module required for a hardware logic simulation; converting an original unit testing into an extended unit testing; using the extended unit testing to perform a unit testing on the wrapper class to thereby produce an input pattern file; and performing the hardware logic simulation on the hardware circuit block in accordance with the top module and the input pattern file.

Abstract: A process of automatically translating a high level programming language into a hardware description language (HDL), which can use a three-stage translation mechanism to generate the HDL codes corresponding to the functions described by the high level programming language. The first stage translates source codes coded by the high level programming language into an extended activity diagram (EAD). The second stage translates the EAD into a hardware component graph (HCG). The third stage generates the respective signal connections of HDL components according to all edges of the HCG, and outputs an HDL entity and architecture to a file in a string form, thereby completing the entire translation.

Abstract: An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.

Abstract: A current equalizer assembly for LCD backlight panel comprises at least a differential current choke and at least a capacitor. The capacitor is arranged striding on a terminal (B) at a primary coil and on a terminal (D) at a secondary coil of the differential current choke so as to equalize the current flowing through every cold cathode fluorescent lamp (CCFL) connected to the differential current choke and the lightness thereof accordingly. Moreover, the capacitance of the stridden capacitor is replaceable by the intrinsic stray capacitance when the inductance of the differential current choke is properly selected.