Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: The subject matter of this specification can be embodied in, among other things, a computer-implemented item identification method that includes identifying an item in an image received from a remote electronic device; transmitting search results containing information about the item for one or more vendors of the item; and transmitting to the remote device code for executing an order for the item from the one or more vendors of the item.

Abstract: An ozone toothbrush is comprised of a main body, a brush head which is provided on one end of the main body and a power connection device which is provided on the other end of the main body. An ozonizer and a gas-pressurized device which can supply ozone generated by the ozonizer to the brush head through a transmission channel are provided in the main body. The brush head can be axially connected to the main body by spiral engagement or insertion, or can be radially connected to the main body by spiral engagement or insertion.

Abstract: A telescopic table board positioned with a resilient pin is provided, which is characterized by the following features: The telescopic table board includes a left table board and a right table board slidely nested with each other; as for the left table board and the right table board, one of them is fixedly provided with a rack, while the other with a corresponding seat bore, in which is a resilient pin positioned, which is mainly composed of a positioning fastener and a spring; the positioning fastener is provided at the head with a tooth head engaged with the corresponding rack, extends at the tail through the seat bore, and is provided at the tail end with a handle; and the spring is sleeved onto the positioning fastener, and functions between the positioning fastener and the seat bore, thus constituting the resilient-pin type telescopic positioning mechanism between the left table board and the right table board.

Abstract: Space is allocated within a table layout for a plurality of items to be placed therein by application of a first rule in which each item is ordered according to increasing column span for the item. Thereafter, a second rule is applied for each ordered item. The second rule recognizes that space need not necessarily be added to the right-most column for an item at issue, and that space needed for the right-most column for an item at issue should be ‘borrowed’ from the next column to the right, presuming such space is available and would not impinge on any other item. Finally, the second rule recognizes that despite everything, situations can arise where there is no elegant way to allocate space for all items within a table layout. In such a circumstance, space is added to the right-most column for the item at issue.

Abstract: An API is provided for positioning items in a table. The API allows a number of columns or a number of rows, or both, to be specified for a table. Any items to be placed in the table may be identified for the API. Items may be “moveable,” or not associated with fixed positions in the table. The moveable items may be placed adjacently in the table to fill a first row. New rows or columns may be generated to accommodate additional items. Items may also be “fixed,” or associated with fixed positions in the table. Moveable items may fill in around the fixed items. A novel algorithm is provided to efficiently place both moveable and fixed items in a table. An on-demand reservation grid may be used in conjunction with the algorithm, thereby accommodating items that span multiple columns and/or rows.

Abstract: A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A memory device comprises a memory array of memory cells for storing data and an information array of information cells for storing operating information. The information array is coupled to the memory array so that the information array and the memory array share the same data path circuitry for reading, erase or programming operations. A power-on control circuit controls the operation of the information array.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A read reference determining the logical value for results read from memory is adjusted during unstable power conditions.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: This invention provides methods for treating and for inhibiting the onset of cancer in a subject comprising administering an agent that inhibits the ability of Sir2? to inhibit p53-dependent apoptosis. This invention also provides a related method for inducing the death of a cell. This invention further provides a method for decreasing the amount of damage to a subject's cells caused by physical stress comprising administering agent that increases the amount of Sir2? in the subject's cells and/or the ability of Sir2? to inhibit p53-dependent apoptosis in the subject's cells. This invention further provides related methods for prolonging the life-span of a subject, decreasing the amount of damage to a cell caused by physical stress, and prolonging the life-span of a cell. Finally, this invention provides two articles of manufacture for performing the instant methods.

Abstract: A nitride trapping memory device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and loading nonvolatile memory data and nonvolatile memory complementary data to a read data register and a read complementary data register, respectively. The nonvolatile memory data and the nonvolatile memory complementary data are compared with the read data register and the read complementary data register during the power on sequence, e.g., after initial power up or power on reset (POR). When the comparison determines a mismatch, the loading of the nonvolatile memory data and the nonvolatile memory complementary data to the read data register and the read complementary data register, respectively, is repeated.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and performing an error bit check on at least one memory cell in the flash memory during initial power up. The at least one memory cell in the flash memory is read only after the error bit check determines that the device voltage is stable. The data read from the at least one memory cell is loaded to an information register.

Abstract: A method of performing a power on sequence for a flash memory includes applying device voltage to the flash memory and performing an error bit check on at least one memory cell in the flash memory during initial power up. The at least one memory cell in the flash memory is read only after the error bit check determines that the device voltage is stable. The data read from the at least one memory cell is loaded to an information register.

Abstract: A nitride read-only memory (NROM) device includes a comparator, a bias unit, a memory cell, a cycling cell, a compensation cell and a control unit. The comparator has a reference voltage. The bias unit is for outputting a bias voltage to the comparator, and the comparator outputs a bit value according to comparison of the bias voltage and the reference voltage. The memory cell is connected to the bias unit via a first switch. The cycling cell is connected to the bias unit via a second switch. The compensation cell is connected to the bias unit via a third switch. The control unit is for controlling the cycling cell and the compensation cell according to the bit value.

Abstract: The present invention relates to a footbath basin with pressure massage function, which comprising a body of footbath basin (11) and an air massage device (14) which comprises a plentiful of independent airbags. In the body of footbath basin (11), a pump (12), an input, and an air guide control device (13) are connected with the outputs of the pump of the body of footbath basin (11), the air guide control device (13) has a plentiful of outputs, at least two of which are connected with the input/output of the varied airbags of the air massage device (14) through an air tubes (17) respectively. The footbath basin with pressure massage function of the present invention may be cooperated with foot health care, and massage the other parts of the whole body simultaneously, enhance the whole blood circulation, make more effective health, and save time simultaneously.