Patents by Inventor Jianbin Zhu
Jianbin Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200379945Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of reconfigurable units that may include a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of reconfigurable units may comprise a configuration buffer and a reconfiguration counter. The processor may further comprise a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of MPs to execute a sequence of instructions.Type: ApplicationFiled: July 17, 2020Publication date: December 3, 2020Inventors: Jianbin Zhu, Yuan Li
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Publication number: 20200379944Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.Type: ApplicationFiled: July 16, 2020Publication date: December 3, 2020Inventors: Jianbin Zhu, Yuan Li
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Patent number: 10850918Abstract: The present invention provides a container having a bottom frame; the bottom frame includes a pair of bottom side rails, a plurality of cross member and a floor. The pair of bottom side rails are located at both sides of the bottom of the container respectively. The plurality of cross members are located between and connected to the bottom side rails. The floor is laid on the cross members and extends along the longitudinal direction of the container; the floor comprises a first steel floor. The bottom frame further includes a grit discharging structure configured to discharge the grits, collected on the upper surface of the first steel floor after the inner surface and/or the welding seam on the inner surface of the container is shot-blasted, from the container.Type: GrantFiled: August 26, 2016Date of Patent: December 1, 2020Assignees: NANTONG CIMC-SPECIAL TRANSPORTATION EQUIPMENT MANUFACTURE CO., LTD, CIMC CONTAINERS HOLDING COMPANY LTD., CHINA INTERNATIONAL MARINE CONTAINERS (GROUP) LTD.Inventors: Jinghua Chen, Zhijun Huang, Xinlin Lu, Xiya Li, Sidong He, Sinming Chen, Jianbin Zhu, Xiaoli Zhao, Suwen Wu
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Publication number: 20200356524Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each PE may have a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.Type: ApplicationFiled: June 19, 2020Publication date: November 12, 2020Inventors: Yuan Li, Jianbin Zhu
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Patent number: 10776310Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.Type: GrantFiled: March 13, 2018Date of Patent: September 15, 2020Assignee: AzurEngine Technologies Zhuhai Inc.Inventors: Yuan Li, Jianbin Zhu
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Patent number: 10776311Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of reconfigurable units that may include a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of reconfigurable units may comprise a configuration buffer and a reconfiguration counter. The processor may further comprise a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of MPs to execute a sequence of instructions.Type: GrantFiled: March 13, 2018Date of Patent: September 15, 2020Assignee: AzurEngine Technologies Zhuhai Inc.Inventors: Jianbin Zhu, Yuan Li
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Patent number: 10776312Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.Type: GrantFiled: March 13, 2018Date of Patent: September 15, 2020Assignee: AzurEngine Technologies Zhuhai Inc.Inventors: Jianbin Zhu, Yuan Li
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Patent number: 10733139Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each PE may have a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.Type: GrantFiled: March 13, 2018Date of Patent: August 4, 2020Assignee: AzurEngine Technologies Zhuhai Inc.Inventors: Yuan Li, Jianbin Zhu
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Publication number: 20200004553Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Yuan Li, Jianbin Zhu
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Patent number: 10084486Abstract: A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.Type: GrantFiled: September 29, 2017Date of Patent: September 25, 2018Assignee: Intel CorporationInventors: Jianbin Zhu, Yi Zhou, Yuzhou Zhang, Yuan Li, Chuong Vu
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Publication number: 20180267809Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise an arithmetic logic unit (ALU), a data buffer associated with the ALU, and an indicator associated with the data buffer to indicate whether a piece of data inside the data buffer is to be reused for repeated execution of a same instruction as a pipeline stage.Type: ApplicationFiled: March 13, 2018Publication date: September 20, 2018Inventors: Yuan Li, Jianbin Zhu
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Publication number: 20180267929Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.Type: ApplicationFiled: March 13, 2018Publication date: September 20, 2018Inventors: Yuan Li, Jianbin Zhu
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Publication number: 20180267930Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of reconfigurable units that may include a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of reconfigurable units may comprise a configuration buffer and a reconfiguration counter. The processor may further comprise a sequencer coupled to the configuration buffer of each of the plurality of reconfigurable units and configured to distribute a plurality of configurations to the plurality of reconfigurable units for the plurality of PEs and the plurality of MPs to execute a sequence of instructions.Type: ApplicationFiled: March 13, 2018Publication date: September 20, 2018Inventors: Jianbin Zhu, Yuan Li
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Publication number: 20180267931Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each PE may have a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a different memory bank in the memory unit.Type: ApplicationFiled: March 13, 2018Publication date: September 20, 2018Inventors: Yuan Li, Jianbin Zhu
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Publication number: 20180267932Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) each having a plurality of arithmetic logic units (ALUs) that are configured to execute a same instruction in parallel threads and a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit. Each of the plurality of MPs may comprise an address calculation unit configured to generate respective memory addresses for each thread to access a common area in the memory unit.Type: ApplicationFiled: March 13, 2018Publication date: September 20, 2018Inventors: Jianbin Zhu, Yuan Li
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Publication number: 20180057251Abstract: The present invention provides a container having a bottom frame; the bottom frame includes a pair of bottom side rails, a plurality of cross member and a floor. The pair of bottom side rails are located at both sides of the bottom of the container respectively. The plurality of cross members are located between and connected to the bottom side rails. The floor is laid on the cross members and extends along the longitudinal direction of the container; the floor comprises a first steel floor. The bottom frame further includes a grit discharging structure configured to discharge the grits, collected on the upper surface of the first steel floor after the inner surface and/or the welding seam on the inner surface of the container is shot-blasted, from the container.Type: ApplicationFiled: August 26, 2016Publication date: March 1, 2018Applicants: NANTONG CIMC-SPECIAL TRANSPORTATION EQUIPMENT MANUFACTURE CO., LTD., CIMC CONTAINERS HOLDING COMPANY LTD., CHINA INTERNATIONAL MARINE CONTAINERS (GROUP) LTD.Inventors: Jinghua CHEN, Zhijun HUANG, Xinlin LU, Xiya LI, Sidong HE, Xinming CHEN, Jianbin ZHU, Xiaoli ZHAO, Suwen WU
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Publication number: 20170015498Abstract: A container has a floor, bottom side beams are arranged to two sides of the floor, bottom cross beams are arranged between the bottom side beams on the two sides, at least the underside of the bottom cross beams is constructed as a closed structure, and/or at least the underside thereof extends only towards the ground. In the container, the underside of the bottom cross beams is free of a location where pests and microorganisms are hidden, thereby eliminating the potential of the pests and microorganisms being attached to the bottom cross beams and spreading everywhere with the container, and meanwhile the investigation of the container is also simplified, contributing to increasing the speed of circulation of containers.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Applicants: NANTONG CIMC-SPECIAL TRANSPORTATION EQUIPMENT MANUFACTURE CO., LTD., CHINA INTERNATIONAL MARINE CONTAINERS (GROUP) LTD., CIMC CONTAINERS HOLDING COMPANY LTD.Inventors: Jianbin ZHU, Guoquan LV, Xinlin LU, Feng WANG, Aijun WANG
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Patent number: 8996948Abstract: Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.Type: GrantFiled: September 10, 2012Date of Patent: March 31, 2015Assignee: Intel CorporationInventors: Jianbin Zhu, Yuan Li, Tao Zhang
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Patent number: 8983008Abstract: Methods and apparatus for trellis termination of a turbo decoder are disclosed which simplifies the hardware implementation. As a given example, backward state metrics, which is required to be calculated with forward state metric as part of a constitute decoding, are initialized with pre-calculated values based on input bits.Type: GrantFiled: December 21, 2010Date of Patent: March 17, 2015Assignee: Intel CorporationInventor: Jianbin Zhu
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Patent number: 8930791Abstract: In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold.Type: GrantFiled: September 10, 2012Date of Patent: January 6, 2015Assignee: Intel CorporationInventors: Yuan Li, Jianbin Zhu, Tao Zhang