Abstract: Methods and apparatus for early stop algorithm of turbo decoding are disclosed. An example method comprises of combination of comparing of hard decisions of soft outputs of the current iteration and the previous iteration and comparing the minimum log likelihood results against a threshold. The decoding iteration is stopped once the hard decisions are matched and the minimum soft decoding result exceeds a threshold.

Abstract: Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

Abstract: According to some embodiments of the invention, a turbo decoder in a Universal Mobile Telecommunication System (UMTS) is provided, the turbo decoder comprising: a plurality of maximum a posteriori (MAP) engines; a first plurality of extrinsic memory banks and a second plurality of extrinsic memory banks; and wherein each of the first and second pluralities of extrinsic memory banks is accessible by at least one of the plurality of MAP engines, and wherein each of the first and second pluralities of extrinsic memory banks is configured to organize data according to a R×C matrix having a format similar to that of an interleaver table. During decoding, the first and second pluralities of extrinsic memory banks may be accessed for data by a MAP engine such that the first and second pluralities of extrinsic memory banks function as an interleaver or a de-interleaver of extrinsic information within the turbo decoder.

Abstract: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

Abstract: Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

Abstract: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

Abstract: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the turbo decoder is operating in HSDPA mode the plurality of extrinsic memory banks is configured such that during a first half of a decoding iteration, the MAP engine is able to read a first dataset from and write second dataset to the plurality of extrinsic memory banks in natural row and column order, and during a second half of the decoding iteration, the MAP engine is able to read a third dataset from and write a fourth dataset to the plurality of extrinsic memory banks in a predetermined row and column order in accordance with an interleaver table using a read column buffer and a write column buffer.

Abstract: In one embodiment, device for early stopping in turbo decoding includes a processor configured to receive a block of data to be decoded, compare hard decision bits resulting from decoding iterations and compare a minimum value of log likelihood ratio (LLR) of decoded bits against a threshold. The processor configured to match hard-decisions with previous iteration results. The processor may be configured to set an early stop rule after the matching hard-decisions with previous iteration results is matched. The processor may be configured to set an early stop rule when the minimum reliability of the output bits exceeds the threshold.

Abstract: Methods and apparatus for tail termination are provided that include a decoder that includes a processor configured to a forward state metric and a backward state metric wherein each iteration of an initial state of the backward state metric is fetched from a memory and is pre-computed without feedback from a decoding iteration. Each decoding iteration is substantially identical, and the backward state metric that is pre-computed is used for a subsequent iteration. The decoder may include a turbo decoder or a radix-4 decoder.

Abstract: Provided are devices, systems and methods for rate matching and de-rate matching on digital signal processors. In one embodiment, a device for rate matching and de-rate matching, includes an interface for receiving a plurality of blocks of data and digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters and receive a set of pre-computed puncturing thresholds. For one or more blocks in the plurality of blocks, the DSP computes a block signature from the pre-computed puncturing thresholds; matches the block signature to one of a set of pre-computed zone signatures, derives a zone index corresponding to the one pre-computed zone signature, and applies pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

Abstract: Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.

Abstract: Methods and apparatus for early stop algorithm of turbo decoding are disclosed. An example method comprises of combination of comparing of hard decisions of soft outputs of the current iteration and the previous iteration and comparing the minimum log likelihood results against a threshold. The decoding iteration is stopped once the hard decisions are matched and the minimum soft decoding result exceeds a threshold.

Abstract: Methods and apparatus for trellis termination of a turbo decoder are disclosed which simplifies the hardware implementation. As a given example, backward state metrics, which is required to be calculated with forward state metric as part of a constitute decoding, are initialized with pre-calculated values based on input bits.

Abstract: A tank container with electronic monitoring device includes a tank barrel and a container frame supporting the same. The tank barrel includes a valve assembly and a valve assembly protection box. The electronic monitoring device is installed inside the valve assembly protection box, or on a sealing surface of the tank barrel, or in a range of the container frame outside the tank barrel. The electronic monitoring device includes a sensor for detecting a leakage condition of the cargoes contained in the tank container and transmitting an information data related to the leakage condition, and a data processing module connected with the sensor for processing the data. The invention can be used for detecting a sealing condition of a sealing surface and an illegal open of a lid of the valve assembly protection box as well as for realizing a global tracking, whereby ensuring a safe transport for containers.

Abstract: A tank container with electronic monitoring device includes a tank barrel and a container frame supporting the same. The tank barrel includes a valve assembly and a valve assembly protection box. The electronic monitoring device is installed inside the valve assembly protection box, or on a sealing surface of the tank barrel, or in a range of the container frame outside the tank barrel. The electronic monitoring device includes a sensor for detecting a leakage condition of the cargoes contained in the tank container and transmitting an information data related to the leakage condition, and a data processing module connected with the sensor for processing the data. The invention can be used for detecting a sealing condition of a sealing surface and an illegal open of a lid of the valve assembly protection box as well as for realizing a global tracking, whereby ensuring a safe transport for containers.