Patents by Inventor Jiandi A. An

Jiandi A. An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240131536
    Abstract: An irrigation spraying device includes: a tee joint, a ground picket, a spraying head and two quick connectors. The spraying head is disposed at a top portion of the tee joint; the two quick connectors are disposed on two sides of the tee joint respectively; and a top portion of the ground picket is provided with an engaging portion, which includes two clips matched with two ends of the tee joint respectively. The device can achieve spray irrigation through hanging, can adapt to various irrigation scenes, improves its adaptability, and is simple in structure, convenient to operate, and suitable for popularization and application. A setting of the clips enables a rotation of the tee joint to realize angle adjustment of the spraying head, thereby adjusting the angle of the spraying head during ground irrigation, further improving the adaptability of the device to meet needs of various irrigation scenes.
    Type: Application
    Filed: August 31, 2023
    Publication date: April 25, 2024
    Inventor: Jiandi MENG
  • Patent number: 11901260
    Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 13, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Yazhou Zhang, Binbin Zheng, Sundarraj Chandran, Wenbin Qu, Chin-Tien Chiu
  • Patent number: 11837476
    Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 5, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
  • Patent number: 11810896
    Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Zengyu Zhou, Rui Yuan, Fen Yu, Hope Chiu
  • Patent number: 11784135
    Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: October 10, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Binbin Zheng, Rui Guo, Chin-Tien Chiu, Zengyu Zhou, Fen Yu
  • Publication number: 20230049100
    Abstract: Provided are methods, system and software for diagnosis, prediction and prognosis of a cancer patient based on the quantitative level of a set of biomarkers. Also provided is a database for the purpose of recording the quantitative level of a set of biomarkers.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 16, 2023
    Inventor: Jiandi ZHANG
  • Publication number: 20230011439
    Abstract: A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.
    Type: Application
    Filed: July 7, 2021
    Publication date: January 12, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu
  • Publication number: 20220415750
    Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.
    Type: Application
    Filed: September 2, 2022
    Publication date: December 29, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jiandi Du, Yazhou Zhang, Binbin Zheng, Sundarraj Chandran, Wenbin Qu, Chin-Tien Chiu
  • Publication number: 20220406726
    Abstract: A semiconductor device has shielding to prevent transmission and/or reception of EMI and/or RFI radiation. The semiconductor device comprises a substrate including grounded contact pads around a periphery of the substrate, exposed at one or more edges of the substrate. A bump made of gold or other non-oxidizing conductive material may be formed on the contact pads, for example using ultrasonic welding to remove an oxidation layer between the contact pads and the conductive bumps. The conductive bumps electrically couple to a conductive coating applied around the periphery of the semiconductor device.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jiandi Du, Binbin Zheng, Rui Guo, Chin-Tien Chiu, Zengyu Zhou, Fen Yu
  • Publication number: 20220375896
    Abstract: A method and apparatus for substrate component layout and bonding for increased package capacity. According to certain embodiments, a wire-bonding finger strip is disposed between a flip-chip die and a NAND die stack to reduce a keep out zone (KOZ) required for an underfill material dispensed beneath the flip-chip die. To further inhibit the flow of the underfill material and further reduce the KOZ, a solder mask may be placed adjacent to the flip-chip. According to certain embodiments, there may be at least three sides of the flip-chip that may have such an adjacent solder mask placement. The three sides of the flip-chip according to such embodiments may be those non-adjacent to the wire-bonding finger strip.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 24, 2022
    Inventors: Jiandi DU, Zengyu ZHOU, Rui YUAN, Fen YU, Hope CHIU
  • Patent number: 11488883
    Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: November 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
  • Publication number: 20220328374
    Abstract: A semiconductor device package includes a substrate, a heat-generating component positioned on a surface of the substrate, and an encapsulant at least partially covering the heat-generating component and having an outer surface. A first heat-conducting layer is disposed between the encapsulant and the first heat-generating component. One or more pillars are in contact with the first heat-conducting layer and extend to the outer surface of the encapsulant and contact a second heat-conducting layer disposed on the outer surface of the encapsulant.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 13, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Jiandi Du, Hope Chiu, Cong Zhang, Fen Yu, Ada Shen, Gary Zheng, Honny Chen
  • Patent number: 11444001
    Abstract: A thermoelectric semiconductor device includes a heat dissipating semiconductor module and a stack of flash memory dies mounted on a substrate. The heat dissipating module comprises a first semiconductor die such as a controller, and a second semiconductor die such as a thermoelectric semiconductor die to cool the first semiconductor die during operation. The thermoelectric semiconductor die may be mounted to the controller die at the wafer level.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: September 13, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jiandi Du, Yazhou Zhang, Binbin Zheng, Sundarraj Chandran, Wenbin Qu, Chin-Tien Chiu
  • Publication number: 20210335628
    Abstract: A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.
    Type: Application
    Filed: May 15, 2020
    Publication date: October 28, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yazhou Zhang, Hope Chiu, Jiandi Du, Paul Qu
  • Patent number: 10907265
    Abstract: A method for growing nanotubes via flow-regulated microfluidic electrochemical anodization, includes providing a microfluidic device having a fluid inlet; a fluid outlet; and a fluidic microchannel connecting the fluid inlet and outlet, wherein the microchannel includes a Pt cathode and a Ti anode separated by an electrical insulator; providing an electrolyte fluid flow through the microchannel; and providing an electrical current across the anode and cathode sufficient to cause electrochemical anodization growth of TiO2 nanotubes in the microchannel on a surface of the anode.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 2, 2021
    Assignee: Rochester Institute of Technology
    Inventors: Jiandi Wan, Rong Fan, Zihao Wang
  • Publication number: 20210011010
    Abstract: Provided is a method for quantitative analysis of a sample. The method includes steps of (a) providing a singular marker representative of one or more features of the sample, the sample comprising a population of individual units of the marker; (b) measuring the marker with dot blot analysis, wherein the quantitation result is an absolute amount of the marker's population of individual units in the sample, normalized by the sample volume or by the sample weight; and (c) obtaining an objective determination of the one or more features of the sample based on the quantitation result of the marker. Also disclosed is a reference database and a method to use the reference database for diagnosing cancer in a patient.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventor: Jiandi Zhang
  • Patent number: 10788484
    Abstract: Provided is a method for quantitative analysis of a sample. The method includes steps of (a) providing a singular marker representative of one or more features of the sample, the sample comprising a population of individual units of the marker; (b) measuring the marker with dot blot analysis, wherein the quantitation result is an absolute amount of the marker's population of individual units in the sample, normalized by the sample volume or by the sample weight; and (c) obtaining an objective determination of the one or more features of the sample based on the quantitation result of the marker. Also disclosed is a reference database and a method to use the reference database for diagnosing cancer in a patient.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 29, 2020
    Assignee: QUANTICISION DIAGNOSTICS INC.
    Inventor: Jiandi Zhang
  • Patent number: 10380223
    Abstract: A support tensor machine based neutral point grounding mode decision method and system adopts a support tensor machine method Based on three indexes, i.e., the power supply reliability index, safety index, and economical efficiency index, influences of different neutral point grounding modes are analyzed by employing the support tensor machine method to finally obtain a neutral point grounding mode capable of maximizing power supply reliability of a distribution network.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 13, 2019
    Assignees: STATE GRID ZHEJIANG ELECTRIC POWER COMPANY LIMITED, STATE GRID ZHEJIANG ECONOMIC RESEARCH INSTITUTE, STATE GRID NINGBO ELECTRIC POWER SUPPLY COMPANY LIMITED, ZHEJIANG HUAYUN ELECTRIC POWER ENGINEERING DESIGN CONSULTING CO. LTD
    Inventors: Yingjing He, Yangqing Dan, Weijun Liu, Weimin Zheng, Xiaodi Zhang, Chaoming Zheng, Xiran Wang, Shuyi Shen, Yan Yao, Yanwei Zhu, Fan Li, Lin Zhou, Jiandi Fang, Dan Yu, Ren Tang
  • Patent number: D898747
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 13, 2020
    Inventor: Jiandi Deng
  • Patent number: D959617
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 2, 2022
    Assignee: YUYAO DINGZHAN INSERT PLASTIC & FITTING CO., LTD.
    Inventor: Jiandi Meng