Abstract: A training data effectiveness evaluation method includes: acquiring a training set, where the training set is acquired by uniform downsampling from target data; acquiring a test set, where the test set includes at least one benchmark test set and at least one correlated test set; training a probe model based on the training set; testing the probe model based on the test set, and recording test metrics; generating an observation plot based on the test metrics, where the generating the observation plot includes: establishing a Cartesian coordinate system with a test metric of the benchmark test set as a horizontal axis and a test metric of the correlated test set as a vertical axis, and plotting key points in the Cartesian coordinate system based on the test metrics; and evaluating effectiveness of the target data based on the observation plot. The present disclosure has the following advantages.

Abstract: A method for communication processing is provided. The method is applicable to a terminal device, where the terminal device is provided with a first subscriber identity module (SIM) card and a second SIM card. The first SIM card and the second SIM card multiplex a hardware resource of the terminal device in a time-division manner. The method includes: obtaining a reception occasion for execution of a non-connected-state service via the second SIM card, when the first SIM card is in a connected state and the second SIM card is in a non-connected state; and determining a connected-state-service gap according to the reception occasion. The terminal device is allowable to execute a connected-state service via the first SIM card in the connected-state-service gap.

Abstract: A method for communication control includes: determining a first number of radio frequency (RF) channels requested by a first communication card and a second number of RF channels requested by a second communication card; in a first preset situation, determining a third number of RF channels and a fourth number of RF channels based on the first number of RF channels and the second number of RF channels; and reporting a first capability and a second capability to a first network device and a second network device, respectively, in which, the first capability indicates that a number of RF channels supported by the first communication card is the third number of RF channels, and the second capability indicates that a number of RF channels supported by the second communication card is the fourth number of RF channels.

Abstract: A voltage attack detection circuit includes: at least one voltage regulation circuit, where the at least one voltage regulation circuit is connected to an external supply respectively, the at least one voltage regulation circuit is configured to convert the external supply to at least one internal supply, and the at least one internal supply is configured to output at least one first voltage respectively; at least one voltage sensor, where the at least one voltage sensor is connected to the at least one internal supply respectively, so as to receive the at least one first voltage respectively, each voltage sensor of the at least one voltage sensor is configured to output a reference voltage based on a received reference voltage and a received first voltage, the reference voltage is configured to indicate whether a received first voltage is within a present voltage range.

Abstract: A voltage attack detection circuit includes at least one voltage regulation circuit, at least one voltage sensor and at least one glitch sensor. The at least one voltage sensor is configured to receive at least one first voltage output by the at least one voltage regulation circuit respectively, and output at least one first signal respectively. The at least one first signal is configured to indicate whether it is under voltage attack of a duration in a first range and an attack strength in a second range respectively. The at least one glitch sensor is configured to receive at least one first voltage respectively, and configured to output at least one second signal respectively. The at least one second signal is configured to indicate whether it is under voltage attack of a duration in a third range and an attack strength in a fourth range.

Abstract: A voltage attack detection circuit of a chip includes: a first programmable resistor and a second programmable resistor, a first terminal of the first programmable resistor is connected to a supply voltage, a second terminal of the first programmable resistor is connected to a ground voltage through the second programmable resistor, the first terminal outputs a first voltage, the second terminal outputs a second voltage; a voltage detection circuit, receives the first voltage and a first reference voltage and output a first signal, where the first signal is configured to indicate whether the first voltage is greater than or equal to the first reference voltage, the voltage detection circuit is further configured to receive the second voltage and a second reference voltage and output a second signal, and the second signal is configured to indicate whether the second voltage is less than or equal to the second reference voltage.

Abstract: A method for communication processing is provided. The method is applicable to a terminal device, where the terminal device is provided with a first subscriber identity module (SIM) card and a second SIM card. The first SIM card and the second SIM card multiplex a hardware resource of the terminal device in a time-division manner. The method includes: obtaining a reception occasion for execution of a non-connected-state service via the second SIM card, when the first SIM card is in a connected state and the second SIM card is in a non-connected state; and determining a connected-state-service gap according to the reception occasion. The terminal device is allowable to execute a connected-state service via the first SIM card in the connected-state-service gap.

Abstract: A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit includes a voltage sampling module, wherein the voltage sampling module includes: a first metal oxide semiconductor MOS transistor and a capacitor for sampling a power supply voltage, wherein a gate terminal of the first MOS transistor is connected to the capacitor, a source terminal of the first MOS transistor is connected to a ground voltage. The power glitch signal detection circuit further comprises a second MOS transistor and a signal output module. One terminal of the second MOS transistor is connected to a gate terminal of the first MOS transistor, another terminal of the second MOS transistor is connected to the power supply voltage, and a drain terminal of the second MOS transistor is connected to a drain terminal of the first MOS transistor.

Abstract: A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit comprises: a latch and a signal output module, wherein a first input of the latch is connected to a power supply voltage, a first output of the latch is connected to a ground voltage, a second input of the latch is connected to a third output of the latch, a third input of the latch is connected to a second output of the latch, and the second output or the third output is connected to the signal output module. The power glitch signal detection circuit could detect a power glitch on the power supply voltage or the ground voltage, and the power glitch signal detection circuit has the advantages of low power consumption, small area, high speed, high sensitivity and strong portability.

Abstract: A power-on reset circuit, including: a band-gap reference circuit, a current comparator, and a voltage comparison circuit powered by a voltage source; a first output terminal of the band-gap reference circuit connects to a control terminal of the current comparator; a first current input terminal and a second current input terminal of the current comparator receives a first current signal and a second current signal respectively, and an output terminal of the current comparator connects to a control terminal of the voltage comparison circuit; and a first input terminal of the voltage comparison circuit connects to the first output terminal of the band-gap reference circuit, a second input terminal thereof receives a signal indicating a voltage value of the voltage source, an output terminal thereof outputs a reset signal, thereby avoiding occurrence of an error caused by output of the reset signal when the reference generating circuit is unstable.

Abstract: A power-on reset circuit, including: a band-gap reference circuit, a current comparator, and a voltage comparison circuit powered by a voltage source; a first output terminal of the band-gap reference circuit connects to a control terminal of the current comparator; a first current input terminal and a second current input terminal of the current comparator receives a first current signal and a second current signal respectively, and an output terminal of the current comparator connects to a control terminal of the voltage comparison circuit; and a first input terminal of the voltage comparison circuit connects to the first output terminal of the band-gap reference circuit, a second input terminal thereof receives a signal indicating a voltage value of the voltage source, an output terminal thereof outputs a reset signal, thereby avoiding occurrence of an error caused by output of the reset signal when the reference generating circuit is unstable.

Abstract: The disclosure provides liposomes (e.g., cancer-targeting liposomes) with ligands (e.g., EGFR ligands and ICAM-1 ligands) conjugated to liposome surfaces. In some embodiments, the molecular ratio of different ligands complement the relative molecular density (i.e., ratio) of overexpressed protein on the surface of a cell targeted by the liposome (e.g., cancer cell).

Abstract: A voltage attack detection circuit includes: at least one voltage regulation circuit, where the at least one voltage regulation circuit is connected to an external supply respectively, the at least one voltage regulation circuit is configured to convert the external supply to at least one internal supply, and the at least one internal supply is configured to output at least one first voltage respectively; at least one voltage sensor, where the at least one voltage sensor is connected to the at least one internal supply respectively, so as to receive the at least one first voltage respectively, each voltage sensor of the at least one voltage sensor is configured to output a reference voltage based on a received reference voltage and a received first voltage, the reference voltage is configured to indicate whether a received first voltage is within a present voltage range.

Abstract: A voltage attack detection circuit of a chip includes: a first programmable resistor and a second programmable resistor, a first terminal of the first programmable resistor is connected to a supply voltage, a second terminal of the first programmable resistor is connected to a ground voltage through the second programmable resistor, the first terminal outputs a first voltage, the second terminal outputs a second voltage; a voltage detection circuit, receives the first voltage and a first reference voltage and output a first signal, where the first signal is configured to indicate whether the first voltage is greater than or equal to the first reference voltage, the voltage detection circuit is further configured to receive the second voltage and a second reference voltage and output a second signal, and the second signal is configured to indicate whether the second voltage is less than or equal to the second reference voltage.

Abstract: A voltage attack detection circuit includes at least one voltage regulation circuit, at least one voltage sensor and at least one glitch sensor. The at least one voltage sensor is configured to receive at least one first voltage output by the at least one voltage regulation circuit respectively, and output at least one first signal respectively. The at least one first signal is configured to indicate whether it is under voltage attack of a duration in a first range and an attack strength in a second range respectively. The at least one glitch sensor is configured to receive at least one first voltage respectively, and configured to output at least one second signal respectively. The at least one second signal is configured to indicate whether it is under voltage attack of a duration in a third range and an attack strength in a fourth range.

Abstract: A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit includes: a voltage sampling module configured to acquire and output a sampled voltage of a power supply voltage; a detection unit array, including multiple MOS transistors with various threshold voltages, wherein first terminals of the multiple MOS transistors are connected to the sampled voltages, and second terminals of the multiple MOS transistors are connected to the power supply voltage; a switch array, including multiple switches corresponding to the multiple MOS transistors; and a signal generation circuit, wherein drain terminals of the multiple MOS transistors are connected to the signal generation circuit through the multiple switches respectively.

Abstract: A detection circuit of electromagnetic fault injection includes: a shielding layer configured to shield interference; at least one group of metal-oxide semiconductor MOS transistors, where a source end of the at least one group of MOS transistors is connected to the shielding layer; at least one latch, where a drain end of the at least one group of MOS transistors is connected to an input end of the at least one latch; and a signal output module, where an input end of the signal output module is connected to an output end of the at least one latch. The detection circuit could detect in real time and alarm electromagnetic fault injection in time to ensure robustness and safety of a chip.