Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit controls to connect or disconnect the input terminal and the first input node under the control of a clock signal provided by the clock signal terminal; the charge pump circuit controls to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.

Abstract: A shift register unit, a method for driving a shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes: a second noise reduction control circuit. The second noise reduction control circuit includes: a first control circuit, configured to transmit a first voltage to a second noise reduction control node; a first coupling circuit, configured to store a level of the second noise reduction control node and adjust the level of the second noise reduction control node; a second coupling circuit, configured to reduce an adjustment magnitude of the first coupling circuit in case of adjusting the level of the second noise reduction control node; a transmission circuit, configured to connect the first noise reduction control node and the second noise reduction control node; and a storage circuit, configured to store the level of the first noise reduction control node.

Abstract: Provided is a display substrate including a display region and a non-display region. The non-display region is provided with a gate drive circuit, and the gate drive circuit includes a plurality of cascaded shift register units; a shift register unit includes an input sub-circuit and a denoising output sub-circuit. The denoising output sub-circuit is connected with the input sub-circuit, a first group of clock signal lines, and a second group of clock signal lines, and the input sub-circuit is connected with a third group of clock signal lines. The third group of clock signal lines, the input sub-circuit, the first group of clock signal lines, the denoising output sub-circuit, and the second group of clock signal lines are sequentially arranged along a first direction.

Abstract: A shift register unit, a driving method thereof, a gate driving circuit and a display panel are provided. The shift register unit includes an input circuit, a reset circuit, a first output circuit and a second output circuit; the input circuit is configured to control a level of a first node in response to a first input signal; the reset circuit is configured to reset the first node in response to a reset signal; the first output circuit is configured to output a shift signal under control of the level of the first node; and the second output circuit is configured to, in a first phase, under control of the level of the first node, output a plurality of sub-pulses at the first output terminal as a first output signal in a case where the shift output terminal outputs a first level of the shift signal.

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a plurality of sub-pixels in rows. The sub-pixels in each row includes first sub-pixels, second sub-pixels and third sub-pixels arranged alternately, and two adjacent rows of sub-pixels are arranged in a staggered manner. In every two adjacent rows of sub-pixels, each first sub-pixel in one row of sub-pixels and the second sub-pixel and the third sub-pixel adjacent to the first sub-pixel in another row of sub-pixels form a pixel. White brightness centers of the pixels in a same pixel row are located on a same straight line, and a brightness center of the first sub-pixel is not on a same straight line as the brightness centers of the second sub-pixel and the third sub-pixel located in a same sub-pixel row.

Abstract: The present disclosure provides a signal generation circuit, a signal generation method, a signal generation module and a display device. The signal generating circuit includes an input terminal, a signal output terminal, a transmission control circuit, a first output circuit, and an output control circuit; the output control circuit is electrically connected to a first output control terminal, a second output control terminal, a second voltage terminal, the signal writing-in terminal, the signal output terminal and the first voltage terminal, configured to control to connect the signal writing-in terminal and the second voltage terminal under the control of a second output control signal provided by the second output control terminal, and control to connect the signal output terminal and the first voltage terminal under the control of a first output control signal provided by the first output control terminal. The present disclosure expands an adjustment range of frequency of a PWM signal.

Abstract: Provided is a display panel. The display panel includes a base substrate, provided with a curved display region and a planar display region, wherein the curved display region is configured for curved display; and a plurality of first sub-pixels disposed in the curved display region and a plurality of second sub-pixels disposed in the planar display region, wherein each of the first sub-pixels and the second sub-pixels includes: a planarization layer, an electrode pattern, a light-emitting pattern, and an electrode layer which are sequentially laminated in a direction going away from the base substrate.

Abstract: A display panel includes: a substrate; at least one first signal line disposed on the substrate and located in a peripheral region; at least one second signal line disposed on the substrate and located in the peripheral region; an insulating layer covering the at least one first signal line and the at least one second signal line; and a shielding signal line covering the at least one groove. The at least one second signal line and the at least one first signal line are arranged in a same layer. A surface of the insulating layer away from the substrate has at least one groove. An orthogonal projection, on the substrate, of a bottom surface of a groove is located between orthogonal projections, on the substrate, of a first signal line and a second signal line.

Abstract: A gate driving unit includes a first input node control circuit and a charge pump circuit; the first input node control circuit is configured to connect or disconnect the between an input terminal and the first input node under control of a clock signal provided by the clock signal terminal; the charge pump circuit is configured to control to convert a voltage signal of the first input node into a voltage signal of the first node under the control of an input clock signal provided by the input clock signal terminal when the voltage signal of the first input node is a first voltage signal, so that a polarity of the voltage signal of the first input is the same as a polarity of the voltage signal of the first input node, and an absolute value of the voltage value of the voltage signal of the first node is greater than an absolute value of a voltage value of the voltage signal of the first input node.

Abstract: An electroluminescent display panel includes a plurality of repeating units each including a first conductive layer, a first insulating layer including a first via hole, and an anode including a main body and an auxiliary portion. At least one repeating unit includes a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel; the area of the main body of the third-color sub-pixel is larger than that of the second-color sub-pixel and that of the first-color sub-pixel; and an overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the second-color sub-pixel and the first conductive layer, and the overlapping area between the main body of the third-color sub-pixel and the first conductive layer is larger than that between the main body of the first-color sub-pixel and the first conductive layer.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a base substrate having pixel regions arranged in an array, each pixel region including a first sub-pixel region and a second sub-pixel region; a light emitting layer and a color conversion layer sequentially stacked on the base substrate; the color conversion layer includes a first color conversion block in at least the first sub-pixel region of at least one pixel region, each of the at least one first color conversion block includes at least two color conversion materials for converting a light component of a color into a light of a target display color, colors of the light components converted by the color conversion materials are different, the target display color is different from the color of the light emitted from the light emitting layer.

Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

Abstract: A shift register circuit includes a denoising control sub-circuit and a denoising sub-circuit. The denoting control sub-circuit is configured to generate an alternating voltage signal according to a voltage of a first voltage terminal and a signal of a second clock signal terminal in response to a signal of a first clock signal terminal, to rectify the alternating voltage signal and then to output a signal to a first denoising control node, so that the voltage of the first denoting control node is maintained to be a voltage that enables the denoising sub-circuit to be turned on. The denoting sub-circuit is configured to denoise a scan signal output terminal in response to a voltage of the first denoising control node being the voltage that enables the denoising sub-circuit to be turned on.

Abstract: Disclosed are a method and apparatus for determining electrical characteristics of a transistor, and a computer-readable storage medium. The method for determining electrical characteristics of a transistor includes: determining mobility characteristics of carriers in channels of the transistor at a transistor operating temperature condition; and determining electrical characteristics of the transistor based on the mobility characteristics of the carriers, semiconductor material properties of the transistor, and structural features of the transistor.

Abstract: A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.

Abstract: Provided are a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a substrate and a plurality of pixel units disposed in matrix on the substrate, wherein each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a driving structure layer, a first electrode and a first pixel define layer on the driving structure layer, and a light absorption layer disposed on the first pixel define layer. The first pixel define layer includes a plurality of first barriers and first pixel openings disposed between the first barriers, the first pixel opening exposes at least part of the first electrode, and the first pixel opening includes a first surface close to the first electrode, a second surface opposite to the first surface and a first sidewall between the first and second surfaces.

Abstract: The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.