Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Abstract: An apparatus and method are described for improving the efficiency of graphics operations in a virtual execution environment.

Abstract: A fan coil unit, including: a blower including a volute, a wind wheel, and a motor; a fan housing; a heat exchanger; and a hydrostatic plate. The volute includes a first chamber, a first air inlet, and a first air outlet. The wind wheel is disposed in the first chamber of the volute. The motor includes an output shaft which extends into the first chamber and is connected to the wind wheel. The fan housing includes a second chamber, a second air inlet, and a second air outlet. The heat exchanger is disposed in the second chamber and is located between the second air inlet and the second air outlet. The volute further includes a volute tongue which is close to the first air outlet. The hydrostatic plate is connected to the volute tongue. The hydrostatic plate includes an upper end and a lower end.

Abstract: Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

Abstract: Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

Abstract: The present invention discloses a method and system for switching an operating state of a robot. The method comprises the following steps of: providing an excitation device for an opening terminal and an excitation device for a closing terminal on a mask of the robot; transmitting, by the excitation device, a mask state signal to a slave computer processor when the mask is opened or closed; by the slave computer processor, processing the received mask state signal and then transmitting the processed mask state signal to a master computer processor; and controlling, by the master computer processor, the switchover of the operating state of the robot according to the received processed mask state signal. With regard to the technical solutions of the present invention, through the opening and closing of a mask, the system of a robot can be in two operating states and perform different functions.

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Abstract: Disclosed is a character editing method for a screen display device. The method comprises: displaying original character information in a character editing area of a screen display device; receiving selection of a to-be-modified character in the original character information; acquiring a candidate replacement character corresponding to the to-be-modified character from a confusable character database; displaying the candidate replacement character in a recommended area of the screen display device; receiving selection of the candidate replacement character; and replacing the to-be-modified character in the original character information by using the selected candidate replacement character. The present application also provides a character editing device for a screen display device.

Abstract: An array substrate and a manufacturing method thereof, a display panel and a display device are provided. The array substrate comprises a base substrate, and a test pad and an alignment film which are formed on the base substrate. A groove is provided on a surface of the test pad, and an extending direction of the groove is consistent with a rubbing direction of the alignment film.

Abstract: Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.

Abstract: Methods, apparatuses and storage medium associated with ISA bridging with callback, are disclosed. In various embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution of the instructions, to provide an ISA bridging layer to the target device to facilitate a library service to callback a callback function of an application. The library service may be implemented for the target ISA, and the application may be implemented at least partially for a source ISA that may be different from the target ISA. The ISA bridging layer may include a source ISA emulator and a library emulator configured to cooperate to enable the application to call the library service, and the library service to callback the callback function, across the two instruction set architectures. Other embodiments may be disclosed or claimed.

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Abstract: An apparatus and method are described for improving the efficiency of graphics operations in a virtual execution environment.

Abstract: Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.

Abstract: Provided is a vertical wafer boat with columns having a rectangular cross section, and capable of making a flow of a film-forming gas between wafer support portions more uniform, suppressing variation in the film thickness in a wafer plane, and forming a more uniform film. A vertical wafer boat includes columns on which wafer support portions for mounting a plurality of wafers are formed, and a top plate and a bottom plate that fix upper and lower end portions of the columns. At least one of the columns includes two column portions and extending in an up and down direction and having a rectangular cross section, and a plurality of the wafer support portions that connects the two column portions and mounts wafers on upper surfaces.

Abstract: The present invention is applicable to the field of the Internet of Things, and provides a method, a node, and a gateway for triggering networking. The method includes receiving, by a node, non-contact trigger induction; and adding the node and a gateway to a same network. The present invention provides a convenient trigger manner to add a node and a gateway to a same network, and ensures that the node is added to a correct network, thereby facilitating a user to perform an operation of triggering networking.

Abstract: A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.