Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Abstract: An integrated circuit includes a first inverter and a first transmission gate constructed with wide type-one transistors and wide type-two transistors. The integrated circuit also includes a first clocked inverter constructed with narrow type-one transistors and narrow type-two transistors. A latch is formed with the first inverter and the first clocked inverter. The first transmission gate is connected to between an output of the first inverter. The wide type-one transistors are formed in a wide type-one active-region structure and the narrow type-one transistors are formed in a narrow type-one active-region structure. The wide type-two transistors are formed in a wide type-two active-region structure and the narrow type-two transistors are formed in in a narrow type-two active-region structure.

Abstract: A monolithic three-dimensional (3D) integrated circuit (IC) device includes a lower tier including a lower tier cell and an upper tier arranged over the lower tier. The upper tier has a first upper tier cell and a second upper tier cell separated by a predetermined lateral space. A monolithic inter-tier via (MIV) extends from the lower tier through the predetermined lateral space, and the MIV has a first end electrically connected to the lower tier cell and a second end electrically connected to the first upper tier cell.

Abstract: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

Abstract: An integrated circuit includes a horizontal routing track in a first metal layer, and a backside routing track in a backside metal layer. The backside metal layer and the first metal layer are formed at opposite sides of a semiconductor substrate. The horizontal routing track is conductively connected to a first terminal of a first transistor without passing through a routing track in another metal layer. The backside routing track is conductively connected to a second terminal of the first transistor without passing through a routing track in another metal layer.

Abstract: A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Abstract: A method includes patterning a substrate to define a semiconductor strip over the substrate; and forming a backside via adjacent to the semiconductor strip. The method further includes depositing a dielectric material. The method further includes etching the dielectric material to define an isolation structure having a top surface lower than a top surface of the semiconductor strip. The method further includes forming a source/drain structure over the semiconductor strip. The method further includes forming an interlayer dielectric layer over the source/drain structure. The method further includes etching the interlayer dielectric layer and the isolation structure to define an opening exposing the backside via. The method further includes forming a source/drain contact in the opening.

Abstract: A flip-flop device includes first through third power rails, a first plurality of conductive patterns positioned at a total of three locations evenly spaced between the first and second power rails, a second plurality of conductive patterns positioned at a total of three locations evenly spaced between the second and third power rails, a master latching circuit including a first subset of each of the first and second pluralities of conductive patterns, a slave latching circuit including a second subset of each of the first and second pluralities of conductive patterns, and a gate conductor extending across at least one of the three locations of the first plurality of conductive patterns and at least one of the three locations of the second plurality of conductive patterns. The gate conductor is configured to transmit one of a first clock signal or a feedback signal of the flip-flop device.

Abstract: A device includes: alternating first rows and second rows correspondingly including first cell regions and second cell regions, each of the first cell regions and second cell regions correspondingly including active regions; in a first metallization layer over the active regions, each of the first cell regions and the second cell regions include first and second power grid (PG) segments, and one or more routing (RTE) segments; and in a first buried metallization layer under the active regions, each of the first cell regions includes first and second buried PG (BPG) segments, and each of the second cell regions includes one or more buried local interconnect (BLI) structures; and each of the first cell regions is free from including a BLI structure.

Abstract: A semiconductor device including a first active area layer that extends in a first direction, a first metal over diffusion layer that extends in a second direction that is different than the first direction, the first metal over diffusion layer situated over the first active area layer, a first gate that extends in the second direction and over the first active area layer, a first gate end of the first gate that abuts a first dielectric region, and first low-k dielectric material situated in the first dielectric region.

Abstract: A device including: a first active region; first and second ohmic-contact layers correspondingly on, and coupled to, a front side and a back side of a first portion of the first active region; a metal-to-source/drain (MD) contact including a first part on the first ohmic-contact layer and at least a second part or a third part correspondingly aside a first lateral side or a second lateral side of the first portion of the first active region, the first part of the MD contact being coupled to the first ohmic-contact layer; and a buried-via (BV) structure including: a first part under, and coupled to, the second ohmic-contact layer; and a second part under, and coupled to, the MD contact.

Abstract: A layout method is provided. A timing analysis is performed based on design data of a standard cell to classify a plurality of device units of the standard cell into a timing-critical group and a non-timing-critical group. A plurality of first sources regions in the device units of the non-timing-critical group are aligned with a plurality of second sources regions in the device units of the timing-critical group in a first direction in floorplan of the standard cell in a layout. The device units of the timing-critical group are arranged in a first row of a cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array. The first and second rows of the cell array share a common power line. First active regions of the first row are wider than second active regions of the second row.

Abstract: An integrated circuit (IC) package includes a first die including first IC devices electrically connected to a first signal routing structure positioned at a first surface and a second surface opposite the first surface, wherein the first die has a first orientation of the first and second surfaces along a first direction, a second die comprising including second IC devices electrically connected to a second signal routing structure positioned at a third surface and a fourth surface opposite the first surface, wherein the second die has a second orientation of the third and fourth surfaces along the first direction opposite the first orientation, and a power distribution structure extending between the second and fourth surfaces and electrically connected to each of the first and second IC devices.

Abstract: An integrated circuit includes frontside power rails in a frontside metal layer above the substrate, backside signal lines in a first backside metal layer below the substrate, backside power rails in a second backside metal layer below the first backside metal layer, and backside via-connectors passing through the substrate. A first frontside power rail and a first backside via-connector are conductively connected to the source terminal of a first-type transistor. A second frontside power rail and a second backside via-connector are conductively connected to the source terminal of a second-type transistor. A first extended via-connector is directly connected between the first backside via-connector and a first backside power rail. A second extended via-connector is directly connected between the second backside via-connector and a second backside power rail.

Abstract: A device includes: a first cell region stacked on a second cell region; each including a first active region over a second active region; in a first layer of metallization (M_first layer) over the first active region, M_first power grid (PG) segments having a first reference voltage and M_first routing segments aligned correspondingly to M_first routing tracks; and in a first layer of metallization (BM_first layer) under the second active region, BM_first PG segments having a second reference, and BM_first routing segments aligned correspondingly to BM_first routing tracks. The M_first routing segments are aligned in the first and second cell regions correspondingly to first (Q1) and second (Q2) quantities of the M_first routing tracks, where Q2<Q1. The BM_first routing segments are aligned in the first and second cell regions correspondingly to third and fourth quantities of the BM_first routing tracks, where Q4<Q3.

Abstract: A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell; forming a plurality of first metal strips on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is located on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall; and forming a plurality of second metal strips on a third plane over the second plane, wherein the plurality of second metal strips comprise a first second metal strip and a second second metal strip separated from each other by the separating wall.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first conductivity type arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second conductivity type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line arranged in a third layer between the first layer and the second layer. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate includes a recess portion, wherein the first conductive line is at an elevation of the recess portion.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes: a first cell, a dielectric layer, and a snorkel structure. The first cell has an output terminal. The dielectric layer is disposed on the first cell. The snorkel structure is disposed in the dielectric layer. The snorkel structure includes a first conductive structure, a first conductive layer, and a second conductive structure. The first conductive layer is electrically connected to the output terminal of the cell. The first conductive layer is disposed on and electrically connected to the first conductive structure. The second conductive structure is disposed on and electrically connected to the first conductive layer. The second conductive structure has a topmost conductive layer buried in the dielectric layer.

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.