Patents by Inventor Jiann-Tyng Tzeng

Jiann-Tyng Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948974
    Abstract: A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng
  • Publication number: 20240104286
    Abstract: The present disclosure provides a method and a non-transitory computer-readable medium for generating a layout of a semiconductor device. The method includes placing a first cell in the layout, providing a polysilicon pattern in the first cell extending along a first direction, designating a plurality of tracks on which metal segments can be placed, the plurality of tracks being across the polysilicon pattern and extending along a second direction different from the first direction. Two adjacent tracks of the plurality of tracks are spaced apart by a first pitch. The method further includes determining whether a number of the tracks in the first cell exceeds a predetermined number, and increasing the first pitch of the tracks so as to decrease the number of the tracks in the first cell to the predetermined number.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Inventors: YEN-HUNG LIN, JIANN-TYNG TZENG
  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Publication number: 20240105601
    Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 28, 2024
    Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU
  • Patent number: 11942470
    Abstract: A semiconductor device includes a first cell. The first cell is surrounded by a castle-shaped forbidden region. The first cell includes a first active region, a second active region, and at least one via. The first active region and the second active region extend along a first direction and are separated from each other along a second direction traverse to the first direction. The first active region partially overlaps an upper region of the castle-shaped forbidden region, and the second active region partially overlaps a lower region of the castle-shaped forbidden region. The at least one via is arranged outside the castle-shaped forbidden region.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11942469
    Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-An Lai, Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang
  • Patent number: 11942413
    Abstract: A semiconductor device includes a substrate having a first side and a second side. The semiconductor device on the first side includes: an active region that extends along a first lateral direction and comprises a first sub-region and a second sub-region; a first gate structure that extends along a second lateral direction and is disposed over the active region, with the first and second sub-regions disposed on opposite sides of the first gate structure, wherein the second lateral direction is perpendicular to the first lateral direction; and a first interconnecting structure electrically coupled to the first gate structure. The semiconductor device on the second side includes a second interconnecting structure that is electrically coupled to the first and second sub-regions and configured to provide a power supply. The active region, the first gate structure, the first interconnecting structure, and the second interconnecting structure are collectively configured as a decoupling capacitor.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng
  • Publication number: 20240096867
    Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
  • Publication number: 20240096805
    Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11935830
    Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Jiun-Wei Lu
  • Patent number: 11935825
    Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Cheng-Chi Chuang, Chih-Ming Lai, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan
  • Patent number: 11923301
    Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, each gate strip is a gate terminal of a transistor; forming a plurality of first contact vias connected to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, each second metal strip and one of the first metal strips are crisscrossed from top view; a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Hui-Ting Yang, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11923297
    Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-An Lai, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11923369
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Wei-Cheng Lin, Wei-An Lai, Jiann-Tyng Tzeng
  • Patent number: 11923273
    Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Chia-Tien Wu, Jiann-Tyng Tzeng
  • Patent number: 11923300
    Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Ken-Hsien Hsieh
  • Patent number: 11916070
    Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Hsin Chiu, Kam-Tou Sio, Shang-Wei Fang, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 11916074
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Publication number: 20240063119
    Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 22, 2024
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Ken-Hsien Hsieh