Patents by Inventor Jiann-Tyng Tzeng

Jiann-Tyng Tzeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387035
    Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Kam-Tou SIO, Cheng-Chi Chuang, Chia-Tien Wu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-Cheng Lin
  • Publication number: 20230385509
    Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei Peng, Lipen Yuan, Jiann-Tyng Tzeng, Wei-Cheng Lin
  • Publication number: 20230387201
    Abstract: A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei PENG, Jiann-Tyng TZENG
  • Publication number: 20230387102
    Abstract: A method (of manufacturing a semiconductor device) includes generating a corresponding layout diagram including: regarding first and second active area patterns which (1) are correspondingly nearest to a boundary between, and (2) are correspondingly in, first and second abutting cells, and for each gate pattern that intersects the first or second active area pattern, selecting the gate patterns for which a first distance from a nearest corresponding via-to-gate (VG) pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each selected gate pattern, relative to a first size, setting a size of a corresponding cut-gate section to a second size; the first size otherwise resulting in an overhang of a gate remnant portion extending towards the boundary by a first length; and the second size resulting in the overhang extending by a second length smaller than the first length.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Te-Hsin CHIU, Shih-Wei PENG, Jiann-Tyng TZENG
  • Publication number: 20230387002
    Abstract: An integrated circuit (IC) structure includes a plurality of first metal segments in a first metal layer of a semiconductor substrate, the plurality of first metal segments corresponding to first tracks, a plurality of second metal segments in a second metal layer of the semiconductor substrate adjacent to the first metal layer, the plurality of second metal segments corresponding to second tracks perpendicular to the first tracks, and a plurality of via structures configured to electrically connect the plurality of first metal segments to the plurality of second metal segments.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Shih-Wei PENG, Chih-Min HSIAO, Ching-Hsu CHANG, Jiann-Tyng TZENG
  • Publication number: 20230376668
    Abstract: A method of generating an IC layout diagram includes overlapping a channel region of an upper transistor of a complementary field-effect transistor (CFET) in an IC layout with a gate region of the CFET, thereby defining a channel overlap region, positioning an isolation region in the IC layout, the isolation region including an entirety of the channel overlap region, intersecting the isolation region with a conductive region, and generating an IC layout diagram based on the IC layout.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Shih-Wei PENG, Guo-Huei WU, Wei-Cheng LIN, Hui-Zhong ZHUANG, Jiann-Tyng TZENG
  • Publication number: 20230377941
    Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 23, 2023
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Publication number: 20230378288
    Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a contact. The first transistor includes a first source/drain (S/D), a second S/D, and a first gate between the first S/D and the second S/D. The first transistor and the second transistor are stacked over the third transistor. The contact covers the second S/D of the first transistor. The contact is electrically connected to the second transistor and electrically isolated from the second S/D.
    Type: Application
    Filed: May 20, 2022
    Publication date: November 23, 2023
    Inventors: SHIH-WEI PENG, CHUN-YEN LIN, WEI-CHENG TZENG, JIANN-TYNG TZENG
  • Publication number: 20230369310
    Abstract: A semiconductor device includes a first cell. The first cell includes: a first source/drain region and a second source/drain region in a first layer; a plurality of gate electrodes in a second layer, the plurality of gate electrodes defining at least one odd-numbered track and at least one even-numbered track; a first power rail extending in a second direction perpendicular to the first direction in a third layer; a first conductive via arranged in a fourth layer, the first conductive via being within a first odd-numbered track and non-overlapped with any of the plurality of gate electrodes from a top-view perspective; a second power rail extending in the second direction in a fifth layer; and a second conductive via arranged in a sixth layer, the second conductive via being within a first even-numbered track and non-overlapped with any of the plurality of gate electrodes from a top-view perspective.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: SHIH-WEI PENG, JIANN-TYNG TZENG
  • Publication number: 20230367950
    Abstract: A complementary field effect transistor (CFET) structure includes a vertical stack of first and second transistors, wherein the first transistor includes a first channel extending in a first direction from a first source/drain (S/D) region to a second S/D region through a gate extending in a second direction perpendicular to the first direction and the second transistor includes a second channel extending in the first direction from a third S/D region to a fourth S/D region through the gate. A first conductive trace extends in the first direction over the gate, a first via extends from the first S/D region to the first conductive trace and is aligned with the third S/D region along the second direction, a second via extends from the fourth S/D region to the first conductive trace, and the first via has a first height greater than a second height of the second via.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Shih-Wei PENG, Jiann-Tyng TZENG, Wei-Cheng LIN
  • Patent number: 11817392
    Abstract: An integrated circuit is disclosed. The integrated circuit includes conductive rails, signal rails, at least one first via, and at least one first conductive segment. The at least one first via is disposed between the first conductive layer and the second conductive layer, and couples a first signal rail of the signal rails to at least one of the conductive rails. The first signal rail is configured to transmit a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first conductive segment is disposed between the first conductive layer and the second conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Peng, Chia-Tien Wu, Jiann-Tyng Tzeng
  • Patent number: 11810949
    Abstract: A method of forming a semiconductor arrangement includes forming a first source pad over a semiconductor layer. A first nanosheet is formed contacting the first source pad. A gate pad is formed adjacent the first nanosheet. A first drain pad is formed over the gate pad and contacting the first nanosheet. A backside interconnect line is formed under the gate pad and the first source pad. A first backside contact is formed contacting at least one of the backside interconnect line, the first source pad, or the gate pad.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11810811
    Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Publication number: 20230352339
    Abstract: A method includes doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.
    Type: Application
    Filed: June 29, 2023
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-An Lai, Jiann-Tyng Tzeng
  • Publication number: 20230354572
    Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.
    Type: Application
    Filed: June 26, 2023
    Publication date: November 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-An Lai
  • Publication number: 20230343708
    Abstract: A semiconductor device, including: a transistor layer, including a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor; a dielectric layer, disposed on the source/drain terminals of the first and second transistors; a conductive strip, included in the dielectric layer and extending from the first active region toward the second active region for signal connection.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: SHIH-WEI PENG, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Publication number: 20230342535
    Abstract: An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region is in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 26, 2023
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG
  • Patent number: 11797746
    Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan, Wei-An Lai
  • Patent number: 11797745
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Ching-Yu Huang, Jiann-Tyng Tzeng
  • Publication number: 20230335485
    Abstract: A semiconductor device includes a base, source, drain and gate electrodes, signal tracks and a power mesh. The source, drain and gate electrodes are arranged on a surface of the base, wherein the gate electrodes are extended along a first direction. The signal tracks arranged above the first surface of the base and above the source and drain electrodes and the gate electrodes, wherein the signal tracks are extended along the first directions. A power mesh is arranged below the first surface of the base, the power mesh comprising first power rails extended in the second direction and second power rails extended in a first direction, wherein the second direction is substantially perpendicular to the first direction.
    Type: Application
    Filed: June 17, 2023
    Publication date: October 19, 2023
    Inventors: WEI-AN LAI, WEI-CHENG LIN, JIANN-TYNG TZENG