Patents by Inventor Jianping Wen

Jianping Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10177779
    Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 8, 2019
    Assignee: AVNERA CORPORATION
    Inventors: Wai Lee, Garry N. Link, Jianping Wen
  • Patent number: 10158373
    Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 18, 2018
    Assignee: AVNERA CORPORATION
    Inventors: Wai Lee, Jianping Wen, Garry N. Link
  • Patent number: 10148280
    Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.
    Type: Grant
    Filed: December 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Avnera Corporation
    Inventors: Wai Lee, Jianping Wen, Garry N. Link
  • Patent number: 10135455
    Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 20, 2018
    Assignee: Avnera Corporation
    Inventors: Jianping Wen, Garry Link, Wai Laing Lee
  • Patent number: 10096312
    Abstract: An adaptive noise canceling system can include a noise cancellation processor having an audio input for receiving an input audio signal, a microphone input structured to receive one or more microphone signals from a monitored environment, and a filter processor structured to produce a filtering function based on one or more filter parameters. The system can also include an adaptivity processor structured to change the one or more filter parameters in the noise cancellation processor based on a changing operating environment of the adaptive noise canceling system.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 9, 2018
    Assignee: AVNERA CORPORATION
    Inventors: Amit Kumar, Wai Laing Lee, Jianping Wen
  • Publication number: 20180278262
    Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 27, 2018
    Inventors: Jianping Wen, Gordon Ueki
  • Publication number: 20180183457
    Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 28, 2018
    Inventors: Wai Lee, Jianping Wen, Garry N. Link
  • Publication number: 20180183456
    Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a comparator to compare sample values of an analog signal in an analog domain to reference values to determine digital values in a digital domain. The digital values correspond to the analog signal and may be determined according to successive approximation. The ADC also includes chop switches to modulate the analog signal to increase a frequency of flicker noise in the analog domain. The ADC also includes an un-chop switch to demodulate the digital values in the digital domain prior filtration of the flicker noise by a digital filter.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 28, 2018
    Inventors: Wai Lee, Garry N. Link, Jianping Wen
  • Publication number: 20180183455
    Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a successive approximation register (SAR) unit including one or more capacitive networks. The capacitive networks take a sample of an analog signal. The SAR also includes a comparator to approximate digital values based on the analog signal sample via successive comparison. The ADC includes a preamplifier coupled to the SAR unit. The preamplifier amplifies the analog signal for application to the capacitive networks for sampling. The ADC also includes a rough buffer coupled to the SAR unit. The rough buffer pre-charges the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier.
    Type: Application
    Filed: December 20, 2017
    Publication date: June 28, 2018
    Inventors: Wai Lee, Jianping Wen, Garry N. Link, Jian Li
  • Publication number: 20180183458
    Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.
    Type: Application
    Filed: December 23, 2017
    Publication date: June 28, 2018
    Inventors: Wai Lee, Jianping Wen, Garry N. Link
  • Publication number: 20180152196
    Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 31, 2018
    Inventors: Jianping Wen, Garry Link, Wai Laing Lee
  • Patent number: 9985640
    Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: May 29, 2018
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Gordon Ueki
  • Publication number: 20180053497
    Abstract: An adaptive noise canceling system can include a noise cancellation processor having an audio input for receiving an input audio signal, a microphone input structured to receive one or more microphone signals from a monitored environment, and a filter processor structured to produce a filtering function based on one or more filter parameters. The system can also include an adaptivity processor structured to change the one or more filter parameters in the noise cancellation processor based on a changing operating environment of the adaptive noise canceling system.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 22, 2018
    Inventors: Amit Kumar, Wai Laing Lee, Jianping Wen
  • Patent number: 9831887
    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive appro
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 28, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Garry Link, Wai Lee
  • Publication number: 20170250703
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 31, 2017
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Patent number: 9741333
    Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: August 22, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Amit Kumar, Wai Lang Lee, Jianping Wen
  • Publication number: 20170126240
    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive appro
    Type: Application
    Filed: December 27, 2016
    Publication date: May 4, 2017
    Inventors: Jianping Wen, Garry Link, Wai Lee
  • Patent number: 9628106
    Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: April 18, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
  • Patent number: 9531400
    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive appro
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: December 27, 2016
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Garry Link, Wai Lee
  • Publication number: 20150195646
    Abstract: A programmable Active Noise Compensation (ANC) system for an audio input includes a parameter store structured to store a number of various filter parameters. A mode of operation is selected that represents the type of environment the ANC system is operating in—feed-forward, feed-back, or combined feed-forward and feedback. Different filter parameters are retrieved from the parameter store based on the selected mode and desired operation. Audio inputs are sampled at a relatively high sample rate that matches inputs from a feed-forward and feedback microphone that may be present in the system. Parameters and instructions may be changed in the system responsive to changing conditions of the compensation system.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: Avnera Corporation
    Inventors: Amit Kumar, Wai Lang Lee, Jianping Wen