Patents by Inventor Jianwei PENG

Jianwei PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910471
    Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jianwei Peng, Sang Woo Lim, Matthew Wahlquist Stoker, Huang Liu, Jinping Liu
  • Patent number: 10836071
    Abstract: The present invention provides a method for processing a molded tray based on bamboo shavings, comprising: extracting, crushing, mixing, drying, separating by wind separation, heat balance treatment, mixing glue, paving and hot pressing, cooling and grinding, inspecting and warehousing. In the invention, the industrial trays are manufactured by bamboo materials. The bamboo materials do not include bamboo peels and other impurities. The use of bamboo materials can improve the quality of trays from raw materials and increase the strength of trays. The industrial trays made by the processing method of the present invention have increased the weight supporting capacity by at least 1.5 times compared to ordinary trays, and the product's service life is 3 to 5 years in normal uses (no water soaking, no overpressure).
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Hangzhou Penno Packtech Co., LTD
    Inventors: Jianwei Peng, Huizhen Jiang
  • Publication number: 20200322237
    Abstract: A traffic detection method includes obtaining a plurality of packets collected by a traffic collection device in a first time period, where the plurality of packets include packets in a first data stream and at least one other data stream collected in the first time period; determining a target feature set based on the plurality of packets, where the target feature set includes a multi-stream feature corresponding to the plurality of packets, and the multi-stream feature includes a statistical parameter about sizes of the plurality of packets; and determining, based on the target feature set and a correspondence between the target feature set and a service type, a service type corresponding to the first data stream collected in the first time period. According to the traffic detection method, more features can be obtained, and accuracy of traffic detection can be improved by using more features.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Inventors: Tao LUO, Jianwei GUO, Liuqing PENG
  • Patent number: 10784342
    Abstract: Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hong Yu, Jianwei Peng, Hui Zhan
  • Patent number: 10773417
    Abstract: The present invention provides a method for processing a molded tray based on bamboo-wood mixed shavings, comprising: extracting, crushing, mixing, drying, separating by wind separation, heat balance treatment, mixing glue, paving and hot pressing, cooling and grinding, inspecting and warehousing. In the invention, the industrial trays are manufactured by mixed bamboo and wood materials. The bamboo materials do not include bamboo peels and other impurities. The use of bamboo materials can improve the quality of trays from raw materials and reduce the moisture content of the trays. In addition, the brittleness of bamboo materials can improve the hardness of trays. The combined bamboo materials and wood materials can increase the toughness of the product and reduce the cost; furthermore, each link in the production process is elaborately designed and adjusted in the invention. The industrial trays made by the processing method of the present invention have increased the weight supporting capacity by at least 1.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 15, 2020
    Assignee: HANGZHOU PENNO PACKTECH CO., LTD
    Inventors: Jianwei Peng, Huizhen Jiang
  • Publication number: 20200287019
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 10, 2020
    Inventors: George R. Mulfinger, Hong Yu, Man Gu, Jianwei Peng, Michael Aquilino
  • Publication number: 20200020769
    Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3x fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3x fin pitch, a TS formed on the RSD, and an ILD formed over the TS.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Jianwei PENG, Sang Woo LIM, Matthew Wahlquist STOKER, Huang LIU, Jinping LIU
  • Publication number: 20200013995
    Abstract: A cell and a battery are provided. The cell includes an electrode assembly and a packaging bag, the electrode assembly includes a first electrode sheet provided with a first coating layer and a first uncoated region, the packaging bag includes a first body, the electrode assembly is disposed in the packaging bag, and the first uncoated region is electrically connected with the first body. Further, the electrode assembly may further include a second electrode sheet provided with a second coating layer and a second uncoated region, the packaging bag may further include a second body, and the second uncoated region is electrically connected with the second body.
    Type: Application
    Filed: January 28, 2019
    Publication date: January 9, 2020
    Inventors: Peipei Guo, Ping He, Yejun Peng, Jianwei Lin, Bin Xie
  • Patent number: 10468310
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jianwei Peng, Xusheng Wu
  • Patent number: 10453754
    Abstract: The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jianwei Peng, Haigou Huang, Qun Gao, Xin Wang
  • Patent number: 10446483
    Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
  • Patent number: 10431665
    Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
  • Patent number: 10410929
    Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie
  • Publication number: 20190221515
    Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.
    Type: Application
    Filed: January 16, 2018
    Publication date: July 18, 2019
    Inventors: Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
  • Publication number: 20190206743
    Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 4, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui ZANG, Jianwei PENG, Yi QI, Hsien-Ching LO, Jerome CIAVATTI, Ruilong XIE
  • Publication number: 20190181243
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 13, 2019
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Patent number: 10297675
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Publication number: 20190131433
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Patent number: 10276689
    Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yi Qi, Jianwei Peng, Hsien-Ching Lo, Ruilong Xie, Xunyuan Zhang, Hui Zang
  • Patent number: D887665
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 16, 2020
    Assignee: Hangzhou Penno Packtech Co., Ltd.
    Inventor: Jianwei Peng