Abstract: An isolation structure for a substrate is disclosed. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.

Abstract: An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

Abstract: Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

Abstract: Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.

Abstract: Disclosed in the present application are a concrete protection material, and a preparation method and a construction method therefor. The concrete protection material consists of 50%-90% of a component A and 10%-50% of a component B in percentage by weight, where the component A is prepared from 30%-65% of organic silicon, 2%-5% of nano-silicon dioxide and the balance of an organic solvent in percentage by weight; and the component B is prepared from 20%-50% of an organic base and the balance of water in percentage by weight. The present application not only can form nano-particles having a strengthening effect in capillary channels of a concrete surface layer, but also can achieve a technical effect of superhydrophobicity on the concrete surface layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

Abstract: A substrate is provided. The substrate includes a base, a semiconductor layer over the base, and an insulator layer between the base and the semiconductor layer. The semiconductor layer has a first semiconductor layer portion having a first thickness, a second semiconductor layer portion having a second thickness, and a third semiconductor layer portion having a third thickness, and the first thickness, the second thickness, and the third thickness are different from each other.

Abstract: The invention provides a modified dolomite powder, a preparation method thereof, and a concrete. The modified dolomite powder is prepared from 98% to 99% of a dolomite powder, 0.2% to 0.5% of a chaotropic agent, 0.6% to 1.0% of a dihydrogen phosphate, and 0.2% to 0.5% of a capillary filler according to the mass percentage. The chaotropic agent is one or more of sodium sulfate, potassium sulfate, and ammonium sulfate. By promoting the dissolution of the surface of the dolomite powder, participating in the hydration reaction, and filling capillary pores, the triple modification solves the problems of bleeding, strength, and durability of the dolomite powder concrete in the related art. The obtained modified dolomite powder has good solubility and high chemical activity, and the prepared concrete has high strength and compactness, low porosity, and good durability.

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

Abstract: Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

Abstract: Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

Abstract: A highly thixotropic 3D printing concrete and a manufacturing method therefor are provided. The weight percentage of each component calculated per cube of concrete is: 35-40% of cement, 0.1-0.4% of polycarboxylate superplasticizer, 0.1-0.4% of polypropylene fiber, 1.0-3.0% of special thixotropic agent for 3D printing concrete, and 12.5-14.5% of water, and the remainder is sand.

Abstract: A highly thixotropic 3D printing concrete and a manufacturing method therefor are provided. The weight percentage of each component calculated per cube of concrete is: 35-40% of cement, 0.1-0.4% of polycarboxylate superplasticizer, 0.1-0.4% of polypropylene fiber, 1.0-3.0% of special thixotropic agent for 3D printing concrete, and 12.5-14.5% of water, and the remainder is sand.

Abstract: An equal-fork pallet comprising a pallet body is provided. The pallet body is provided with a stand structure and a reinforcing structure, the reinforcing structure is a reinforcing rib embodied by a groove structure pressed on the surface of the pallet body, and the reinforcing rib comprises a connection type reinforcing rib and a semi-partition type reinforcing rib, the stand structure comprises a corner stand, an edge stand and a center stand, and neither end of the partition type reinforcing rib is connected to the stand. The equal-fork pallet has a reasonable structural design and strong pressure bearing capacity, with targeted layout and design of the reinforcing rib centralized position and stress concentration position such as stand. The pallet can overcome the problems of low local compressive strength and proneness to produce stress fracture and local cracking.

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.