Patents by Inventor Jianwei PENG
Jianwei PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10773417Abstract: The present invention provides a method for processing a molded tray based on bamboo-wood mixed shavings, comprising: extracting, crushing, mixing, drying, separating by wind separation, heat balance treatment, mixing glue, paving and hot pressing, cooling and grinding, inspecting and warehousing. In the invention, the industrial trays are manufactured by mixed bamboo and wood materials. The bamboo materials do not include bamboo peels and other impurities. The use of bamboo materials can improve the quality of trays from raw materials and reduce the moisture content of the trays. In addition, the brittleness of bamboo materials can improve the hardness of trays. The combined bamboo materials and wood materials can increase the toughness of the product and reduce the cost; furthermore, each link in the production process is elaborately designed and adjusted in the invention. The industrial trays made by the processing method of the present invention have increased the weight supporting capacity by at least 1.Type: GrantFiled: April 24, 2018Date of Patent: September 15, 2020Assignee: HANGZHOU PENNO PACKTECH CO., LTDInventors: Jianwei Peng, Huizhen Jiang
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Publication number: 20200287019Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.Type: ApplicationFiled: March 8, 2019Publication date: September 10, 2020Inventors: George R. Mulfinger, Hong Yu, Man Gu, Jianwei Peng, Michael Aquilino
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Publication number: 20200020769Abstract: A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3x fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3x fin pitch, a TS formed on the RSD, and an ILD formed over the TS.Type: ApplicationFiled: July 11, 2018Publication date: January 16, 2020Inventors: Jianwei PENG, Sang Woo LIM, Matthew Wahlquist STOKER, Huang LIU, Jinping LIU
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Patent number: 10468310Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.Type: GrantFiled: October 26, 2016Date of Patent: November 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Jianwei Peng, Xusheng Wu
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Patent number: 10453754Abstract: The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.Type: GrantFiled: June 28, 2018Date of Patent: October 22, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Jianwei Peng, Haigou Huang, Qun Gao, Xin Wang
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Patent number: 10446483Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.Type: GrantFiled: January 16, 2018Date of Patent: October 15, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
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Patent number: 10431665Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.Type: GrantFiled: January 19, 2018Date of Patent: October 1, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Tao Han, Zhenyu Hu, Jinping Liu, Hsien-Ching Lo, Jianwei Peng
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Patent number: 10410929Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.Type: GrantFiled: January 3, 2018Date of Patent: September 10, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie
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Publication number: 20190221515Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.Type: ApplicationFiled: January 16, 2018Publication date: July 18, 2019Inventors: Sipeng Gu, Jianwei Peng, Xusheng Wu, Yi Qi, Jeffrey Chee
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Publication number: 20190206743Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.Type: ApplicationFiled: January 3, 2018Publication date: July 4, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Hui ZANG, Jianwei PENG, Yi QI, Hsien-Ching LO, Jerome CIAVATTI, Ruilong XIE
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Publication number: 20190181243Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.Type: ApplicationFiled: February 14, 2019Publication date: June 13, 2019Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
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Patent number: 10297675Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.Type: GrantFiled: October 27, 2017Date of Patent: May 21, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
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Publication number: 20190131433Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.Type: ApplicationFiled: October 27, 2017Publication date: May 2, 2019Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
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Patent number: 10276689Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.Type: GrantFiled: June 7, 2017Date of Patent: April 30, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Yi Qi, Jianwei Peng, Hsien-Ching Lo, Ruilong Xie, Xunyuan Zhang, Hui Zang
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Patent number: 10262903Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.Type: GrantFiled: June 22, 2017Date of Patent: April 16, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Judson R. Holt, Yi Qi, Hsien-Ching Lo, Jianwei Peng
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Publication number: 20190103319Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.Type: ApplicationFiled: October 3, 2017Publication date: April 4, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Yi Qi, Hsien-Ching Lo, Jianwei Peng, Wei Hong, Yanping Shen, Yongjun Shi, Hui Zang, Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh
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Patent number: 10249538Abstract: Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.Type: GrantFiled: October 3, 2017Date of Patent: April 2, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Yi Qi, Hsien-Ching Lo, Jianwei Peng, Wei Hong, Yanping Shen, Yongjun Shi, Hui Zang, Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-chen Yeh
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Publication number: 20190092523Abstract: The present invention discloses an equal-fork pallet comprising a pallet body, wherein the pallet body is provided with a stand structure and a reinforcing structure, the reinforcing structure is a reinforcing rib embodied by a groove structure pressed on the surface of the pallet body, and the reinforcing rib comprises a connection type reinforcing rib and a semi-partition type reinforcing rib, the stand structure comprises a corner stand, an edge stand and a center stand, and neither end of the partition type reinforcing rib is connected to the stand. The present invention has a reasonable structural design and strong pressure bearing capacity, with targeted layout and design of the reinforcing rib centralized position and stress concentration position such as stand. It can overcome the problems of the prior art, such as low local compressive strength of the pallet, proneness to produce stress fracture and local cracking, etc.Type: ApplicationFiled: September 26, 2018Publication date: March 28, 2019Inventors: Qiaoli WU, Jianwei PENG, Huizhen JIANG
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Publication number: 20190081155Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content is controlled such that recessed regions created by partial removal of the silicon germanium layers have uniform lateral dimensions, and the backfilling of such recessed regions with an etch selective material results in the formation of a robust etch barrier.Type: ApplicationFiled: September 13, 2017Publication date: March 14, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Ruilong XIE, Kangguo CHENG, Nicolas LOUBET, Xin MIAO, Pietro MONTANINI, John ZHANG, Haigou HUANG, Jianwei PENG, Sipeng GU, Hui ZANG, Yi QI, Xusheng WU
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Patent number: D887665Type: GrantFiled: December 12, 2017Date of Patent: June 16, 2020Assignee: Hangzhou Penno Packtech Co., Ltd.Inventor: Jianwei Peng