Patents by Inventor Jianwen Xu
Jianwen Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140339712Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.Type: ApplicationFiled: May 20, 2013Publication date: November 20, 2014Applicant: QUALCOMM IncorporatedInventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Jianwen Xu
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Patent number: 8841168Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.Type: GrantFiled: May 9, 2013Date of Patent: September 23, 2014Assignee: QUALCOMM IncorporatedInventors: Mark Wendell Schwarz, Jianwen Xu
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Publication number: 20140255333Abstract: The invention relates to materials comprising siloxanes, preferably the materials have thermal-responsive properties. In some embodiments, the invention relates to silsesquioxane groups functionalized with polymers. In another embodiment, silsequioxane-polymer conjugates comprise polylactone segments. The silsequioxane-polymer conjugates may be crosslinked together to form a material, and these materials may be functionalized with bioactive compounds so that the materials have desirable biocompatibility or bioactivity when used in medical devices. In further embodiments, the invention relates to composite materials that contain a polymer matrix and aggregates, and in some embodiments, methods of making, and methods of using these materials. Preferably, the aggregates are calcium phosphate aggregates. Preferably, the material is resistant to fracture. In further embodiments, the materials are used in surgical procedures of bone replacement.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: University of Massachusetts Medical SchoolInventors: Jie Song, Jianwen Xu
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Patent number: 8765112Abstract: The invention relates to materials comprising siloxanes, preferably the materials have thermal-responsive properties. In some embodiments, the invention relates to silsesquioxane groups functionalized with polymers. In another embodiment, silsequioxane-polymer conjugates comprise polylactone segments. The silsequioxane-polymer conjugates may be crosslinked together to form a material, and these materials may be functionalized with bioactive compounds so that the materials have desirable biocompatibility or bioactivity when used in medical devices. In further embodiments, the invention relates to composite materials that contain a polymer matrix and aggregates, and in some embodiments, methods of making, and methods of using these materials. Preferably, the aggregates are calcium phosphate aggregates. Preferably, the material is resistant to fracture. In further embodiments, the materials are used in surgical procedures of bone replacement.Type: GrantFiled: April 18, 2008Date of Patent: July 1, 2014Assignee: University of MassachusettsInventors: Jie Song, Jianwen Xu
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Publication number: 20140058058Abstract: The invention generally relates to functional polymers and hydrogels. More particularly, the invention provides versatile monomers and polymers with well-defined functionalities, e.g., polycarbonates and poly(ester-carbonates), compositions thereof, and methods for making and using the same. The invention also provides cytocompatible poly(ethylene glycol)-co-polycarobonate hydrogels (e.g., crosslinked by copper-free, strain-promoted “click” chemistry).Type: ApplicationFiled: February 24, 2012Publication date: February 27, 2014Applicant: University of Massachusetts Medical SchoolInventors: Jie Song, Jianwen Xu
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Patent number: 8617935Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.Type: GrantFiled: August 30, 2011Date of Patent: December 31, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Jianwen Xu, Zhiwei Gong, Scott M. Hayes
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Patent number: 8609471Abstract: A structure (46) for holding an integrated circuit (IC) die (50) during packing includes a flexible structurally reinforced silicone adhesive film (22) and a mold frame (44). The mold frame (44) adheres to an adhesive side (38) of the film (22). A method (20) of packaging the IC die (50) includes placing the IC die (50) on the adhesive film (22) with its active surface (52) and bond pads (54) in contact with an adhesive side (38) of the film (22). A molding compound (58) is dispensed over the IC die, and the IC die (50) is encapsulated using compression molding to form a compression molded encapsulant layer (70). IC die (50) is subsequently released from the film (22) as a panel (72) of IC dies (50).Type: GrantFiled: February 29, 2008Date of Patent: December 17, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Jianwen Xu
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Patent number: 8597630Abstract: The invention relates to materials comprising polymer network containing siloxanes or organic-based core structures, preferably the materials have thermal-responsive properties. In some embodiments, the invention relates to an organic core functionalized with polymers. In another embodiment, organic core-polymer conjugates comprise polylactone segments. The organic core-polymer conjugates may be crosslinked together to form a material, and these materials may be functionalized with bioactive compounds so that the materials have desirable biocompatibility or bioactivity when used in medical devices. In some embodiments, the invention relates to silsesquioxane groups functionalized with polymers. In another embodiment, silsequioxane-polymer conjugates comprise polylactone segments.Type: GrantFiled: March 26, 2010Date of Patent: December 3, 2013Assignee: University of MassachusettsInventors: Jie Song, Jianwen Xu
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Publication number: 20130244384Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.Type: ApplicationFiled: May 9, 2013Publication date: September 19, 2013Applicant: QUALCOMM IncorporatedInventors: Mark Wendell Schwarz, Jianwen Xu
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Patent number: 8461676Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.Type: GrantFiled: September 9, 2011Date of Patent: June 11, 2013Assignee: QUALCOMM IncorporatedInventors: Mark Wendell Schwarz, Jianwen Xu
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Publication number: 20130062746Abstract: A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: QUALCOMM INCORPORATEDInventors: Mark Wendell Schwarz, Jianwen Xu
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Publication number: 20130052777Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.Type: ApplicationFiled: August 30, 2011Publication date: February 28, 2013Inventors: Jianwen Xu, Zhiwei Gong, Scott M. Hayes
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Publication number: 20130015566Abstract: A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.Type: ApplicationFiled: July 14, 2011Publication date: January 17, 2013Inventors: ZHIWEI GONG, Jianwen Xu, Wei Gao, Scott M. Hayes
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Patent number: 8327532Abstract: Methods for forming a microelectronic assembly (82) are provided. In one embodiment, the method includes providing a device substrate (50) having a plurality of electronic components (42) coupled thereto, and providing a carrier substrate (54) having first and second opposing surfaces (60, 62) and including a plurality of openings (58) extending between the first and second opposing surfaces (60, 62) and a plurality of depressions (64) formed on the first opposing surface (60). The method further includes attaching the device substrate (50) to the first opposing surface (60) of the carrier substrate (54) using an adhesive material (56) such that at least some of the adhesive material (56) is adjacent to at least some of the plurality of depressions (64), and removing the device substrate (50) from the carrier substrate (54).Type: GrantFiled: November 23, 2009Date of Patent: December 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Jianwen Xu, Scott M. Hayes, William H. Lytle
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Patent number: 8236609Abstract: A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).Type: GrantFiled: August 1, 2008Date of Patent: August 7, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi N. Ramanathan, Craig S. Amrine, Jianwen Xu
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Patent number: 8216918Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.Type: GrantFiled: July 23, 2010Date of Patent: July 10, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Zhiwei Gong, Scott M. Hayes, George R. Leal, Douglas G. Mitchell, Jason R. Wright, Jianwen Xu
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Publication number: 20120021565Abstract: A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.Type: ApplicationFiled: July 23, 2010Publication date: January 26, 2012Inventors: Zhiwei Gong, Scott M. Hayes, George R. Leal, Douglas G. Mitchell, Jason R. Wright, Jianwen Xu
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Publication number: 20110119910Abstract: Methods and system for forming a microelectronic assembly (82) are provided. A device substrate (50) having a plurality of electronic components (42) coupled thereto is provided. A carrier substrate (54) having first and second opposing surfaces (60, 62) and including a plurality of openings (58) extending between the first and second opposing surfaces (60, 62) and a plurality of depressions (64) formed on the first opposing surface (60) is provided. The device substrate (50) is attached to the first opposing surface (60) of the carrier substrate (54) using an adhesive material (56) such that at least some of the adhesive material (56) is adjacent to at least some of the plurality of depressions (64).Type: ApplicationFiled: November 23, 2009Publication date: May 26, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jianwen Xu, Scott M. Hayes, William H. Lytle
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Publication number: 20100280561Abstract: The invention relates to materials comprising polymer network containing siloxanes or organic-based core structures, preferably the materials have thermal-responsive properties. In some embodiments, the invention relates to an organic core functionalized with polymers. In another embodiment, organic core-polymer conjugates comprise polylactone segments. The organic core-polymer conjugates may be crosslinked together to form a material, and these materials may be functionalized with bioactive compounds so that the materials have desirable biocompatibility or bioactivity when used in medical devices. In some embodiments, the invention relates to silsesquioxane groups functionalized with polymers. In another embodiment, silsequioxane-polymer conjugates comprise polylactone segments.Type: ApplicationFiled: March 26, 2010Publication date: November 4, 2010Inventors: Jie Song, Jianwen Xu
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Publication number: 20100252919Abstract: An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation.Type: ApplicationFiled: April 7, 2009Publication date: October 7, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jianwen Xu, Lizabeth Ann Keser, Goerge R. Leal, Betty H. Yeung