Patents by Inventor Jia-Wei Yang

Jia-Wei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240312557
    Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.
    Type: Application
    Filed: February 16, 2024
    Publication date: September 19, 2024
    Applicant: MEDIATEK INC.
    Inventors: Che-Wei Chou, Ya-Ting Yang, Shu-Lin Lai, Chi-Kai Hsieh, Yi-Ping Kuo, Chi-Hao Hong, Jia-Jing Chen, Yi-Te Chiu, Jiann-Tseng Huang
  • Patent number: 11795437
    Abstract: Disclosed herein is a method for cultivating primary human pulmonary alveolar epithelial cells (HPAEpiC), which includes cultivating the primary HPAEpiC in a first medium containing a basal medium, a culture supplement, and a Rho kinase inhibitor, and a second medium containing the basal medium and the culture supplement in sequence. The culture supplement includes Jagged-1 (JAG-1) peptide, human Noggin protein, transforming growth factor-? (TGF-?) type I receptor inhibitor SB431542, human fibroblast growth factor 7 (hFGF-7), hFGF-10, and glycogen synthase kinase 3 (GSK-3) inhibitor CHIR99021. Also disclosed is a method for preparing a three-dimensional cell culture of alveolar epithelium using the first medium and the second medium.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: October 24, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Guan-Yu Chen, Jia-Wei Yang
  • Patent number: 11732230
    Abstract: A biomimetic system is provided for evaluating an effect of a test sample in vitro, and includes at least one organ chip, at least one medium container, a liquid pump, a nebulizer, a gas pump, and a chamber device. The liquid pump is provided to drive a liquid medium in the medium container to flow into a lower sub-channel of the organ chip and then to be discharged back into the medium container. The nebulizer is provided for atomizing a test solution including the test sample into an aerosol. The gas pump is provided to generate a pressurized gas which force the aerosol to flow out of a chamber of the chamber device and then to flow through an upper sub-channel of the organ chip.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 22, 2023
    Assignee: National Chiao Tung University
    Inventors: Guan-Yu Chen, Jia-Wei Yang, Ko-Chih Lin
  • Publication number: 20220372445
    Abstract: Disclosed herein is a method for cultivating primary human pulmonary alveolar epithelial cells (HPAEpiC), which includes cultivating the primary HPAEpiC in a first medium containing a basal medium, a culture supplement, and a Rho kinase inhibitor, and a second medium containing the basal medium and the culture supplement in sequence. The culture supplement includes Jagged-1 (JAG-1) peptide, human Noggin protein, transforming growth factor-? (TGF-?) type I receptor inhibitor SB431542, human fibroblast growth factor 7 (hFGF-7), hFGF-10, and glycogen synthase kinase 3 (GSK-3) inhibitor CHIR99021. Also disclosed is a method for preparing a three-dimensional cell culture of alveolar epithelium using the first medium and the second medium.
    Type: Application
    Filed: October 8, 2021
    Publication date: November 24, 2022
    Inventors: Guan-Yu Chen, Jia-Wei Yang
  • Patent number: 11385956
    Abstract: A computer-implemented method is presented for detecting anomalies in dynamic datasets generated in a cloud computing environment. The method includes monitoring a plurality of cloud servers receiving a plurality of data points, employing a two-level clustering training module to generate micro-clusters from the plurality of data points, each of the micro-clusters representing a set of original data from the plurality of data points, employing a detecting module to detect normal data points, abnormal data points, and unknown data points from the plurality of data points via a detection model, employing an evolving module using a different evolving mechanism for each of the normal, abnormal, and unknown data points to evolve the detection model, and generating a system report displayed on a user interface, the system report summarizing the micro-cluster information.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jia Wei Yang, Fan Jing Meng
  • Publication number: 20210238522
    Abstract: A biomimetic system is provided for evaluating an effect of a test sample in vitro, and includes at least one organ chip, at least one medium container, a liquid pump, a nebulizer, a gas pump, and a chamber device. The liquid pump is provided to drive a liquid medium in the medium container to flow into a lower sub-channel of the organ chip and then to be discharged back into the medium container. The nebulizer is provided for atomizing a test solution including the test sample into an aerosol. The gas pump is provided to generate a pressurized gas which force the aerosol to flow out of a chamber of the chamber device and then to flow through an upper sub-channel of the organ chip.
    Type: Application
    Filed: June 11, 2020
    Publication date: August 5, 2021
    Inventors: Guan-Yu Chen, Jia-Wei Yang, Ko-Chih Lin
  • Publication number: 20210117259
    Abstract: A computer-implemented method is presented for detecting anomalies in dynamic datasets generated in a cloud computing environment. The method includes monitoring a plurality of cloud servers receiving a plurality of data points, employing a two-level clustering training module to generate micro-clusters from the plurality of data points, each of the micro-clusters representing a set of original data from the plurality of data points, employing a detecting module to detect normal data points, abnormal data points, and unknown data points from the plurality of data points via a detection model, employing an evolving module using a different evolving mechanism for each of the normal, abnormal, and unknown data points to evolve the detection model, and generating a system report displayed on a user interface, the system report summarizing the micro-cluster information.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Inventors: Jia Wei Yang, Fan Jing Meng
  • Patent number: 10949283
    Abstract: A computer-implemented method is presented for detecting anomalies in dynamic datasets generated in a cloud computing environment. The method includes monitoring a plurality of cloud servers receiving a plurality of data points, employing a two-level clustering training module to generate micro-clusters from the plurality of data points, each of the micro-clusters representing a set of original data from the plurality of data points, employing a detecting module to detect normal data points, abnormal data points, and unknown data points from the plurality of data points via a detection model, employing an evolving module using a different evolving mechanism for each of the normal, abnormal, and unknown data points to evolve the detection model, and generating a system report displayed on a user interface, the system report summarizing the micro-cluster information.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jia Wei Yang, Fan Jing Meng
  • Publication number: 20200142763
    Abstract: A computer-implemented method is presented for detecting anomalies in dynamic datasets generated in a cloud computing environment. The method includes monitoring a plurality of cloud servers receiving a plurality of data points, employing a two-level clustering training module to generate micro-clusters from the plurality of data points, each of the micro-clusters representing a set of original data from the plurality of data points, employing a detecting module to detect normal data points, abnormal data points, and unknown data points from the plurality of data points via a detection model, employing an evolving module using a different evolving mechanism for each of the normal, abnormal, and unknown data points to evolve the detection model, and generating a system report displayed on a user interface, the system report summarizing the micro-cluster information.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Inventors: Jia Wei Yang, Fan Jing Meng
  • Patent number: 10147093
    Abstract: The present disclosure provides a system and a method for cash flow verification by a third-party payment platform. The system includes a server and a client device. The client device includes a network device, a storage device and a processor. The storage device is configured to store a plurality of programmed instructions and establish a client database. The processor is configured to execute the programmed instructions to generate execution history data, wherein the execution history data comprises cash flow history data, which can be produced by a third-party platform. While the network device is incapable of connecting the server through the Internet, the processor stores the execution history data in the client database; while the network device is capable of connecting the server through the Internet, the processor transmits the execution history data to the server through the network device for verification, and the verification comprises cash flow verification.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL GAMES SYSTEM CO., LTD.
    Inventors: Jia-Wei Yang, Shih-Ming Chang
  • Publication number: 20170308878
    Abstract: The present disclosure provides a mobile payment system and a mobile payment method. The mobile, payment system includes an e-commerce platform, a connected device and a mobile device. The connected device has a display, the display is configured to show a multimedia content, the multimedia content includes at least a predetermined pattern, and the predetermined pattern corresponds to a virtual goods. The mobile device has an image-capturing device, and the image-capturing device is configured to capture the predetermined pattern from the display, such that the mobile device can obtain buying information on the virtual goods based on the predetermined pattern, so as to process an instant online transaction of the virtual goods through the e-commerce platform.
    Type: Application
    Filed: August 10, 2016
    Publication date: October 26, 2017
    Inventors: Jia-Wei YANG, Sheng-Lun LIN
  • Publication number: 20170161740
    Abstract: The present disclosure provides a system and a method for cash flow verification by a third-party payment platform. The system includes a server and a client device. The client device includes a network device, a storage device and a processor. The storage device is configured to store a plurality of programmed instructions and establish a client database. The processor is configured to execute the programmed instructions to generate execution history data, wherein the execution history data comprises cash flow history data, which can be produced by a third-party platform. While the network device is incapable of connecting the server through the Internet, the processor stores the execution history data in the client database; while the network device is capable of connecting the server through the Internet, the processor transmits the execution history data to the server through the network device for verification, and the verification comprises cash flow verification.
    Type: Application
    Filed: March 29, 2016
    Publication date: June 8, 2017
    Inventors: Jia-Wei YANG, Shih-Ming CHANG
  • Patent number: 7476934
    Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 13, 2009
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Da-Pong Chang, Chih-Cherng Liao
  • Patent number: 7242070
    Abstract: A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: July 10, 2007
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Chih-Cherng Liao
  • Publication number: 20060220117
    Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on an N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.
    Type: Application
    Filed: May 26, 2006
    Publication date: October 5, 2006
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Da-Pong Chang, Chih-Cherng Liao
  • Patent number: 7074658
    Abstract: A structure for an LDMOS transistor has a horseshoe-shaped gate layer formed on a N-type layer of a semiconductor silicon substrate, in which the gate layer comprises a transverse-extending area, a first lengthwise-extending area connected to a left end of the transverse-extending area and a second lengthwise-extending area connected to a right end of the transverse-extending area. A first P-type body is formed in the N-type layer, and overlaps the left periphery of the first lengthwise-extending area of the gate layer. A second P-type body is formed in the N-type layer, and overlaps the right periphery of the second lengthwise-extending area of the gate layer.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: July 11, 2006
    Assignee: Vanguard International Semiconductor Corporatio
    Inventors: Jia-Wei Yang, Da-Pong Chang, Chih-Cherng Liao
  • Patent number: 7041572
    Abstract: A fabrication method for a semiconductor device. On a semiconductor silicon substrate with a first type conductivity, an epitaxial layer with a second type conductivity and an oxide layer on the epitaxial layer are formed with at least a deep trench. Ion implantation is used to form an ion diffusion region with the first type conductivity which is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An oxide liner is formed on the sidewall and bottom of the deep trench, and then an undoped polysilicon layer is formed to fill the deep trench. The combination of the ion diffusion region and the undoped polysilicon layer serves as a deep trench isolation structure.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: May 9, 2006
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Chih-Cherng Liao
  • Publication number: 20060027890
    Abstract: A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 9, 2006
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Chih-Cherng Liao
  • Patent number: 6972471
    Abstract: A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: December 6, 2005
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jia-Wei Yang, Chih-Cherng Liao
  • Publication number: 20050202638
    Abstract: A method of reducing substrate step height. The method includes providing a substrate having a low-voltage device area and high-voltage device area divided by an isolation structure, forming an oxidation mask at least approximately 500 ? thick over the low-voltage device area and parts of the isolation structure, forming a first oxide layer on the exposed high-voltage device area and isolation structure using the oxidation mask as a mask, removing the oxidation mask, and forming a second oxide layer, thinner than the first oxide layer, on the low-voltage device layer.
    Type: Application
    Filed: March 11, 2004
    Publication date: September 15, 2005
    Inventors: Jia-Wei Yang, Da-Pong Chang