Abstract: Methods for depositing layers on substrates are provided herein. In some embodiments, a method of forming a layer on a substrate having at least one feature disposed therein includes forming a conformal layer on an upper surface of the substrate and within the at least one feature by sputtering a target material using a first plasma that reduces the surface energy of the target material such that the sputtered target material wets the upper surface of the substrate and the at least one feature to form the conformal layer; and filling at least a portion of the at least one feature by sputtering the target material using a second plasma different from the first plasma to increase the surface energy of the sputtered target material and the conformal layer such that at least portions of the conformal layer are pulled into the at least one feature by capillary action.

Abstract: Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.

Abstract: An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. Modification of an upper portion of a metal seed layer allows for filling of the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free.

Abstract: Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Abstract: A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.

Abstract: An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. The presence of non-copper pre-electroplating material on the side walls allows the feature whose side walls, but not bottom surface, are lined with such pre-electroplating material (such as cobalt) to fill the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free.

Abstract: A plasma processing chamber particularly useful for pre-treating low-k dielectric films and refractory metal films subject to oxidation prior to deposition of other layers. A remote plasma source (RPS) excites a processing gas into a plasma and delivers it through a supply tube to a manifold in back of a showerhead faceplate. The chamber is configured for oxidizing and reducing plasmas in the same or different processes when oxygen and hydrogen are selectively supplied to the RPS. The supply tube and showerhead may be formed of dielectric oxides which may be passivated by a water vapor plasma from the remote plasma source. In one novel process, a protective hydroxide coating is formed on refractory metals by alternating neutral plasmas of hydrogen and oxygen.

Abstract: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device including forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350° C. to 400° C. for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150° C. to 300° C. for a time duration between about 24 to about 400 hours.

Abstract: Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

Abstract: Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.

Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.

Abstract: A plasma processing chamber particularly useful for pre-treating low-k dielectric films and refractory metal films subject to oxidation prior to deposition of other layers. A remote plasma source (RPS) excites a processing gas into a plasma and delivers it through a supply tube to a manifold in back of a showerhead faceplate. The chamber is configured for oxidizing and reducing plasmas in the same or different processes when oxygen and hydrogen are selectively supplied to the RPS. The supply tube and showerhead may be formed of dielectric oxides which may be passivated by a water vapor plasma from the remote plasma source. In one novel process, a protective hydroxide coating is formed on refractory metals by alternating neutral plasmas of hydrogen and oxygen.

Abstract: A plasma processing chamber particularly useful for pre-treating low-k dielectric films and refractory metal films subject to oxidation prior to deposition of other layers. A remote plasma source (RPS) excites a processing gas into a plasma and delivers it through a supply tube to a manifold in back of a showerhead faceplate. The chamber is configured for oxidizing and reducing plasmas in the same or different processes when oxygen and hydrogen are selectively supplied to the RPS. The supply tube and showerhead may be formed of dielectric oxides which may be passivated by a water vapor plasma from the remote plasma source. In one novel process, a protective hydroxide coating is formed on refractory metals by alternating neutral plasmas of hydrogen and oxygen.

Abstract: Methods for depositing layers on substrates are provided herein. In some embodiments, a method of forming a layer on a substrate having at least one feature disposed therein includes forming a conformal layer on an upper surface of the substrate and within the at least one feature by sputtering a target material using a first plasma that reduces the surface energy of the target material such that the sputtered target material wets the upper surface of the substrate and the at least one feature to form the conformal layer; and filling at least a portion of the at least one feature by sputtering the target material using a second plasma different from the first plasma to increase the surface energy of the sputtered target material and the conformal layer such that at least portions of the conformal layer are pulled into the at least one feature by capillary action.

Abstract: Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device includings forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350° C. to 400° C. for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150° C. to 300° C. for a time duration between about 24 to about 400 hours.

Abstract: Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film.

Abstract: A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.

Abstract: In one embodiment, a method for fabricating a damascene structure is provided which includes exposing a dielectric surface on a substrate to a nitrogen plasma to form a nitrided dielectric layer, wherein the dielectric surface contains a plurality of openings therein, depositing a barrier layer on the nitrided dielectric surface, and depositing a seed layer over the barrier layer. In some examples, the nitrogen plasma is formed from nitrogen gas or a mixture of nitrogen gas and hydrogen gas. The nitrogen plasma may be formed in a barrier deposition chamber or by a reactive preclean chamber. In another embodiment, a bulk layer may be deposited to fill the openings after depositing the seed layer. In one example, the bulk layer may contain copper, tungsten, or alloys thereof, and be deposited by an electrochemical plating process.

Abstract: A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.

Abstract: Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.