Abstract: Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film.

Abstract: A plasma processing chamber particularly useful for pre-treating low-k dielectric films and refractory metal films subject to oxidation prior to deposition of other layers. A remote plasma source (RPS) excites a processing gas into a plasma and delivers it through a supply tube to a manifold in back of a showerhead faceplate. The chamber is configured for oxidizing and reducing plasmas in the same or different processes when oxygen and hydrogen are selectively supplied to the RPS. The supply tube and showerhead may be formed of dielectric oxides which may be passivated by a water vapor plasma from the remote plasma source. In one novel process, a protective hydroxide coating is formed on refractory metals by alternating neutral plasmas of hydrogen and oxygen.

Abstract: A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.

Abstract: An integrated sputtering method and reactor for copper or aluminum seed layers in which a plasma sputter reactor initially deposits a thin conformal layer onto a substrate including a high-aspect ratio hole subject to the formation of overhangs. After the seed deposition, the same sputter reactor is used to sputter etch the substrate with energetic light ions, especially helium, having an energy sufficiently low that it selectively etches the metallization to the heavier underlying barrier layer, for example, copper over tantalum or aluminum over titanium. An RF inductive coil generates the plasma during the sputtering etching while the target power is turned off. A final copper flash step deposits copper over the bare barrier field region before copper is electrochemically plated to fill the hole. The invention also includes a simultaneous sputter deposition and sputter etch, and an energetic ion processing of the copper seed sidewall.

Abstract: A method and apparatus for forming layers on a substrate comprising depositing a metal seed layer on a substrate surface having apertures, depositing a transition metal layer over the copper seed layer, and depositing a bulk metal layer over the transition metal layer. Also a method and apparatus for forming a via through a dielectric to reveal metal at the base of the via, depositing a transition metal layer, and depositing a first metal layer on the transition metal layer. Additionally, a method and apparatus for depositing a transition metal layer on an exposed metal surface, and depositing a layer thereover selected from the group consisting of a capping layer and a low dielectric constant layer.

Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.

Abstract: A first method is provided for forming a barrier layer on a substrate by sputter-depositing a tantalum nitride layer on a substrate having (1) a metal feature formed on the substrate; (2) a dielectric layer formed over the metal feature; and (3) a via formed in the dielectric layer so as to expose the metal feature. The via has side walls and a bottom, and a width of about 0.18 microns or less. The tantalum nitride layer is deposited on the side walls and bottom of the via and on a field region of the dielectric layer; and has a thickness of at least about 200 angstroms on the field region. The first method also includes sputter-depositing a tantalum layer on the substrate, in the same chamber. The tantalum layer having a thickness of less than about 100 angstroms on the field region. Other aspects are provided.

Abstract: A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.

Abstract: Integration of annealing capability into a metal deposition tool or a chemical mechanical polishing (CMP) tool. A wafer processing apparatus includes a metal deposition tool having annealing capability. The metal deposition tool can be an electroplating tool or a chemical vapor deposition tool or other metal deposition tool that deposits metal films, such as copper, onto silicon substrates for integrated circuit manufacturing. An annealing chamber is integrated into the metal deposition tool so that annealing of the metal film can be controlled such that the copper is consistently stabilized in preparation for a chemical mechanical polishing process. Alternatively, an annealing chamber can be integrated into a CMP tool.

Abstract: A process of forming a via through a inter-level dielectric layer and the product. The via is formed by etching a via hole through the inter-level dielectric layer in an area overlying a conductive feature, such a lower copper metallization. Atomic layer deposition (ALD) forms a very thin refractory metal nitride barrier layer over the sidewalls and bottom of the via. Its thickness is less than 1.5 nm, and may be formed with no more than six ALD cycle. A copper seed layer is sputtered onto the barrier including the bottom portion, and copper is electrochemically filled into the hole. The barrier is thin enough to have a low electrical resistance, as may be explained by electronic quantum mechanical tunneling. Further, the crystallography and defects of the underlying copper continue across the thin barrier into the overlying copper.

Abstract: A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.

Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200° C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.

Abstract: Integration of annealing capability into a metal deposition tool or a chemical mechanical polishing (CMP) tool. A wafer processing apparatus includes a metal deposition tool having annealing capability. The metal deposition tool can be an electroplating tool or a chemical vapor deposition tool or other metal deposition tool that deposits metal films, such as copper, onto silicon substrates for integrated circuit manufacturing. An annealing chamber is integrated into the metal deposition tool so that annealing of the metal film can be controlled such that the copper is consistently stabilized in preparation for a chemical mechanical polishing process. Alternatively, an annealing chamber can be integrated into a CMP tool.

Abstract: A method and apparatus for electrochemically plating on a production surface of a substrate are provided. The apparatus generally includes a plating cell having a plating solution reservoir configured to contain a volume of an electrochemical plating solution, and a substrate support member positioned above the plating solution reservoir, the substrate support member being configured to electrically engage a non-production side of a substrate secured thereto.

Abstract: A first method is provided for forming a barrier layer on a substrate by sputter-depositing a tantalum nitride layer on a substrate having (1) a metal feature formed on the substrate; (2) a dielectric layer formed over the metal feature; and (3) a via formed in the dielectric layer so as to expose the metal feature. The via has side walls and a bottom, and a width of about 0.18 microns or less. The tantalum nitride layer is deposited on the side walls and bottom of the via and on a field region of the dielectric layer; and has a thickness of at least about 200 angstroms on the field region. The first method also includes sputter-depositing a tantalum layer on the substrate, in the same chamber. The tantalum layer having a thickness of less than about 100 angstroms on the field region. Other aspects are provided.

Abstract: A method for forming an aluminum or aluminum alloy plug in the fabrication of a semiconductor device. An opening is formed in a wafer. A titanium wetting layer is then deposited over the wafer and lines the sidewalls and bottom of the opening. The opening is then filled with aluminum in two steps, both steps being performed at approximately the same temperature. The first aluminum deposition step is performed at a first (slower) deposition rate. The second aluminum deposition step is performed at the same temperature as the first deposition step but at a different (or second/faster) deposition rate until the opening is completely filled.

Abstract: A conductor fill technique uses an intermetallic compound wetting layer to allow a subsequent conductive material to be reflowed with minimized interaction between the conductive layer and the wetting layer. As one example, a wetting layer including TiAl or TiAl.sub.3 may be formed over a semiconductor wafer and in an opening of the wafer. A conductive layer including aluminum (Al) may then be deposited and reflowed over the wafer to fill the opening in forming a contact, via, or interconnect line, for example, with minimized interaction between the aluminum (Al) of the conductive layer and the wetting layer. Any reduction in conductance of the material filled in the opening may be minimized as the formation of any new intermetallic TiAl.sub.3 compounds that would otherwise increase the resistance of the material filled in the opening is minimized.

Abstract: A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.

Abstract: A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.