Abstract: The current disclosure relates to methods of forming a vanadium nitride-containing layer. The method comprises providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber. The disclosure further relates to structures and devices comprising the vanadium nitride-containing layer.

Abstract: Disclosed are an unblocking apparatus for a furnace discharging pipe and a use method. The unblocking apparatus includes a rail, a rail car that may move along the rail, an unblocking drive mechanism arranged on the rail car, a heat-unblocking component, a cold-unblocking component, and a material receiving component that is used to receive a blocking material in the discharging pipe, and a drive end of the unblocking drive mechanism is detachably connected with one end of the heat-unblocking component and the cold-unblocking component respectively. The present application effectively handles different blockage situations of the furnace discharging pipe by connecting the unblocking drive mechanism with an unblocking rod capable of heat-unblocking and a drilling rod capable of cold-unblocking, thereby two modes of heat-unblocking and cold-unblocking are performed on the furnace discharging pipe; and the discharging pipe may be unblocked by a remote operation.

Abstract: A method for improving message storage efficiency of a network chip, a device, and a storage medium are provided. The method comprises: configuring a data memory, dividing the data memory into N small RAMs, and managing respective RAMs by means of a link list; in a case where a write data request is received on any input interface, parsing and acquiring a channel number corresponding to the input interface, accessing a channel write state memory according to the channel number to acquire channel write state information, in a case of determining, according to the channel write state information, that at least one RAM is null, writing data into the data memory; and in a case where a read-out scheduling request is received on any channel, recombining data according to memory information in a link list memory and reading the recombined data out.

Abstract: A user equipment assistance information (UAI) negotiation method, for a user equipment (UE) of mobile communication includes receiving a first OtherConfig element of an RRC reconfiguration message comprising a plurality of configuration parameters with SETUP values from a network terminal; sending a first UAI including a first value of a first configuration parameter of the configuration parameters to the network terminal; and receiving a first RRC reconfiguration message corresponding to the first UAI from the network terminal.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: An electrical connector includes at least one electrical module. The electrical module includes: an insulating body, where multiple first accommodating slots are concavely provided on a first side toward a second side of the insulating body; multiple first terminal assemblies, respectively accommodated in the corresponding first accommodating slots; and a first grounding member, having multiple first spokes and multiple second spokes. Each first terminal assembly includes a first insulating block, a pair of first signal terminals, and a first shielding shell. Each first shielding shell has a first shielding side surface exposed to the first side. Each first spoke is in mechanical contact with the first shielding shells of a same electrical module, and each second spoke is in contact with the first shielding side surface of the corresponding first shielding shell, thus achieving conduction between the first shielding shells and the first grounding member.

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a first gate line, a second gate line, and a first auxiliary gate portion. The semiconductor substrate comprises a semiconductor fin. The semiconductor fin extends substantially along a first direction. The first gate line and the second gate line extend substantially along a second direction different form the first direction from a top view. The first auxiliary gate portion connects the first gate line to the second gate line from the top view.

Abstract: A semiconductor device includes a semiconductor channel. The semiconductor device includes a metal gate structure disposed over the semiconductor channel. The semiconductor device includes a gate electrode having a bottom surface contacting an upper surface of the metal gate structure. The gate electrode has its side portions extending from its top surface toward the semiconductor fin with a first depth and a central portion extending from its top surface toward the semiconductor fin with a second depth, the first depth being substantially greater than the second depth.

Abstract: A MEMS device is provided. The MEMS device includes a substrate having at least one contact, a first dielectric layer disposed on the substrate, at least one metal layer disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the metal layer and having a recess structure, and a structure layer disposed on the second dielectric layer and having an opening. The opening is disposed on and corresponds to the recess structure, and the cross-sectional area at the bottom of the opening is smaller than the cross-sectional area at the top of the recess structure. The MEMS device also includes a sealing layer, and at least a portion of the sealing layer is disposed in the opening and the recess structure. The second dielectric layer, the structure layer, and the sealing layer define a chamber.

Abstract: The present invention provides a probe device comprising an inner cutting probe and an outer cutting probe. wherein the outer cutting probe has a first side cutting and sucking port in communication with a sliding channel thereof, and the inner probe is slidable within the sliding channel of the outer cutting probe and shaped to have a first end blade edge, a second side port with a second side blade edge and a third side blade edge opposite to the second side blade edge in a cross-sectional view thereof. When the inner cutting probe is slidable within the sliding channel of the outer cutting probe in the forward and backward direction of one cutting cycle, three cuttings are achieved in the forward and backward direction of one cutting cycle, thereby improving the cutting efficiency of the operation.

Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over a first portion of the fin structure, and an epitaxial region formed in a second portion of the fin structure. The epitaxial region can include a first semiconductor layer and an n-type second semiconductor layer formed over the first semiconductor layer. A lattice constant of the first semiconductor layer can be greater than that of the second semiconductor layer.

Abstract: A method for compact and flat bismuth metal preparation by electrolysis is provided. In the method, one or more of ?-naphthol, acacia, sulfonated and vulcanized alkylphenol ethoxylate and naphthol ethoxylate oxides are added to the acidic solution of bismuth methanesulfonate as additives, and the cathodic bismuth is obtained by electrolysis at 20-80° C. The method for bismuth metal preparation is simple and easy to promote, environment-friendly, and the obtained bismuth metal has a flat and compact surface and good plate formation effect.

Abstract: Methods of forming a vanadium nitride-containing layer comprise providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber.

Abstract: In one general aspect, a method can include forming a recess and a mesa in a metal layer associated with a substrate, and disposing a first portion of a conductive-bonding component on the mesa and a second portion of the conductive-bonding component in the recess. The method can include disposing a semiconductor component on the conductive-bonding component such that the second portion of the conductive-bonding component is disposed between an edge of the semiconductor component and a bottom surface of the recess.

Abstract: A package includes a semiconductor die attached to a substrate and a molded body encapsulating the semiconductor die. The molded body is a six-sided rectangular box-like structure and at least a corner portion of the molded body formed by two adjacent sides is devoid of molding material reducing a size and a weight of the molded body.

Abstract: Disclosed are methods and related systems for forming a structure. Embodiments of presently described methods comprise employing a sacrificial gap filling fluid for selectively forming a first layer on one or more first surfaces in a lower part of a gap, and forming a second layer on one or more second surfaces in an upper part of a gap.

Abstract: Vapor deposition methods and related systems are provided for depositing layers comprising vanadium and oxygen. In some embodiments, the methods comprise contacting a substrate in a reaction space with alternating pulses of a vapor-phase vanadium precursor and a vapor-phase oxygen reactant. The reaction space may be purged, for example, with an inert gas, between reactant pulses. The methods may be used to fill a gap on a substrate surface. Reaction conditions, including deposition temperature and reactant pulse and purge times may be selected to achieve advantageous gap fill properties. In some embodiments, the substrate on which deposition takes place is maintained at a relatively low temperature, for example between about 50° C. and about 185° C.

Abstract: A connecting member of a universal connector includes a first insertion hole and a second insertion hole formed on from a first end surface toward a second end surface of the connecting member, and a third insertion hole and a fourth insertion hole formed on the second end surface toward the first end surface of the connecting member, whereby the insertion holes will not be affected by and damage other structures of the connecting member in the mechanical process, so as to achieve the enhancement of the convenience of processing.

Abstract: In one general aspect, an apparatus can include a semiconductor component, a substrate including a recess, and a conductive-bonding component. The conductive-bonding component is disposed between the semiconductor component and the substrate. The conductive-bonding component has a first thickness between a bottom of the recess and a bottom surface of the semiconductor component greater than a second thickness between the top of the substrate and the bottom surface of the semiconductor component.