Patents by Inventor Jie Chang

Jie Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015566
    Abstract: A vertical-cavity surface-emitting laser array includes a substrate. The VCSEL array also includes an active layer formed between a lower mirror and an upper mirror. The VCSEL array also includes a contact layer formed between the active layer and the substrate. The VCSEL array also includes an isolation trench between the first VCSEL and the second VCSEL of the VCSEL array. The isolation trench extending through the contact layer is filled with a filler.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventors: Kai-Jie CHANG, Wan-Ting CHIEN, Yu-Chun CHEN, Chia-Ta CHANG, Jeng-Lin WU
  • Publication number: 20240398142
    Abstract: An anti-tremor device including a tool unit, a carrying portion, and an anti-tremor module is disclosed. The tool unit is coupled or mounted on the carrying portion. The anti-tremor module is disposed on the carrying portion. The anti-tremor module includes a rotary transmission mechanism and a control module. The control module includes a sensing unit and a control unit. The sensing unit is coupled to the control unit, and the control module is coupled to the rotary transmission mechanism. When the sensing unit senses the tremor of the carrying portion, the control unit controls the rotary transmission mechanism to increase the inertia of the anti-tremor module to eliminate or reduce the tremor of the carrying portion.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Inventor: Di-Jie CHANG
  • Patent number: 12159788
    Abstract: Methods and systems for depositing rare earth metal carbide containing layers on a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process such as an atomic layer deposition process for depositing a rare earth metal carbide containing layer onto a surface of the substrate.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: December 3, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Maart van Druenen, Charles Dezelah, Qi Xie, Petro Deminskyi, Giuseppe Alessio Verni, Ren-Jie Chang, Lifu Chen
  • Patent number: 12119576
    Abstract: Implementations of semiconductor packages may include: one or more die electrically coupled to a lead frame. The lead frame may be included within a housing. The semiconductor package may also include a set of signal leads extending from the housing, a set of power leads extending from the housing, and a plurality of press fit pins each fixedly coupled to the set of signal leads and the set of power leads. The set of signal leads and the set of power leads may be configured to couple with a substrate.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: October 15, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie Chang, Huibin Chen, Tiburcio Maldo, Keunhyuk Lee
  • Publication number: 20240312855
    Abstract: A package includes a semiconductor die attached to a substrate and a mold body encapsulating the semiconductor die. A first portion of a lead is directly bonded to a contact pad on the semiconductor die with no intervening component between the first portion of the lead and the contact pad. A second portion of the lead extends outside the mold body to form an external terminal of the package. The lead is a dual gauge lead with the first portion of the lead having a thickness perpendicular to the contact pad that is smaller than a thickness of the second portion of the lead extending outside the mold body.
    Type: Application
    Filed: March 17, 2023
    Publication date: September 19, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: XiaoYing YUAN, Jie CHANG, Keunhyuk LEE
  • Patent number: 12089757
    Abstract: An anti-tremor device including a tool unit, a carrying portion, and an anti-tremor module is disclosed. The tool unit is coupled or mounted on the carrying portion. The anti-tremor module is disposed on the carrying portion. The anti-tremor module includes a rotary transmission mechanism and a control module. The control module includes a sensing unit and a control unit. The sensing unit is coupled to the control unit, and the control module is coupled to the rotary transmission mechanism. When the sensing unit senses the tremor of the carrying portion, the control unit controls the rotary transmission mechanism to increase the inertia of the anti-tremor module to eliminate or reduce the tremor of the carrying portion.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 17, 2024
    Assignee: iCanInnoTech Co., Ltd.
    Inventor: Di-Jie Chang
  • Publication number: 20240304529
    Abstract: Implementations of high-power semiconductor device modules are described, including automotive power transistor assemblies for use in power amplifier circuits such as a cascode circuit. In some implementations, power amplifier circuit components are provided on separate semiconductor die attached to discrete dual die attach pads. A separation between the die attach pads, as well as a through-hole, provide sufficient isolation between the die to permit operation of the circuit at high voltages without relying on a thick multi-layer direct bond copper (DBC) isolation structure. In some implementations, higher voltage operation can be supported by a thin multi-layer, resin coated copper DAP in which the top layer is split.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 12, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie CHANG, XiaoYing YUAN, Keunhyuk LEE, Jerome TEYSSEYRE, Leo GU
  • Patent number: 12031206
    Abstract: Disclosed are methods and systems for depositing layers comprising a transition metal and a group 13 element. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: July 9, 2024
    Assignee: ASM IP Holding, B.V.
    Inventors: Maart van Druenen, Qi Xie, Charles Dezelah, Petro Deminskyi, Lifu Chen, Giuseppe Alessio Verni, Ren-Jie Chang
  • Patent number: 12009224
    Abstract: Devices and methods for selectively etching a metal nitride layer are disclosed. The methods comprise an oxidation step and an etching step which are optionally separated by a purge, and which can be repeated in a cyclical etching process.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 11, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Ren-Jie Chang, Giuseppe Alessio Verni, Qi Xie
  • Publication number: 20240150892
    Abstract: The current disclosure relates to methods of forming a vanadium nitride-containing layer. The method comprises providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber. The disclosure further relates to structures and devices comprising the vanadium nitride-containing layer.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 9, 2024
    Inventors: Pia Homm Jara, Werner Knaepen, Dieter Pierreux, Bert Jongbloed, Panagiota Arnou, Ren-Jie Chang, Qi Xie, Giuseppe Alessio Verni, Gido van der Star
  • Patent number: 11898243
    Abstract: Methods of forming a vanadium nitride-containing layer comprise providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 13, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Pia Homm Jara, Werner Knaepen, Dieter Pierreux, Bert Jongbloed, Panagiota Arnou, Ren-Jie Chang, Qi Xie, Giuseppe Alessio Verni, Gido van der Star
  • Publication number: 20240030093
    Abstract: In one general aspect, a method can include forming a recess and a mesa in a metal layer associated with a substrate, and disposing a first portion of a conductive-bonding component on the mesa and a second portion of the conductive-bonding component in the recess. The method can include disposing a semiconductor component on the conductive-bonding component such that the second portion of the conductive-bonding component is disposed between an edge of the semiconductor component and a bottom surface of the recess.
    Type: Application
    Filed: October 2, 2023
    Publication date: January 25, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Leo GU, Sixin JI, Jie CHANG, Keunhyuk LEE, Yong LIU
  • Publication number: 20240021487
    Abstract: A package includes a semiconductor die attached to a substrate and a molded body encapsulating the semiconductor die. The molded body is a six-sided rectangular box-like structure and at least a corner portion of the molded body formed by two adjacent sides is devoid of molding material reducing a size and a weight of the molded body.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 18, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie CHANG, XiaoYing YUAN, Keunhyuk LEE, Paolo BILARDO
  • Publication number: 20230386934
    Abstract: Disclosed are methods and related systems for forming a structure. Embodiments of presently described methods comprise employing a sacrificial gap filling fluid for selectively forming a first layer on one or more first surfaces in a lower part of a gap, and forming a second layer on one or more second surfaces in an upper part of a gap.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 30, 2023
    Inventors: Shaoren Deng, Marko Tuominen, Vincent Vandalon, Eva E. Tois, Viraj Madhiwala, YongGyu Han, Daniele Chiappe, Michael Givens, Ren-Jie Chang, Giuseppe Alessio Verni, Timothee Blanquart, René Henricus Jozef Vervuurt
  • Publication number: 20230357924
    Abstract: Vapor deposition methods and related systems are provided for depositing layers comprising vanadium and oxygen. In some embodiments, the methods comprise contacting a substrate in a reaction space with alternating pulses of a vapor-phase vanadium precursor and a vapor-phase oxygen reactant. The reaction space may be purged, for example, with an inert gas, between reactant pulses. The methods may be used to fill a gap on a substrate surface. Reaction conditions, including deposition temperature and reactant pulse and purge times may be selected to achieve advantageous gap fill properties. In some embodiments, the substrate on which deposition takes place is maintained at a relatively low temperature, for example between about 50° C. and about 185° C.
    Type: Application
    Filed: April 28, 2023
    Publication date: November 9, 2023
    Inventors: Eric James Shero, Charles Dezelah, Ren-Jie Chang, Qi Xie, Perttu Sippola, Petri Raisanen
  • Publication number: 20230313841
    Abstract: A connecting member of a universal connector includes a first insertion hole and a second insertion hole formed on from a first end surface toward a second end surface of the connecting member, and a third insertion hole and a fourth insertion hole formed on the second end surface toward the first end surface of the connecting member, whereby the insertion holes will not be affected by and damage other structures of the connecting member in the mechanical process, so as to achieve the enhancement of the convenience of processing.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Inventor: Tung-Jie Chang
  • Patent number: 11776871
    Abstract: In one general aspect, an apparatus can include a semiconductor component, a substrate including a recess, and a conductive-bonding component. The conductive-bonding component is disposed between the semiconductor component and the substrate. The conductive-bonding component has a first thickness between a bottom of the recess and a bottom surface of the semiconductor component greater than a second thickness between the top of the substrate and the bottom surface of the semiconductor component.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 3, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Leo Gu, Sixin Ji, Jie Chang, Keunhyuk Lee, Yong Liu
  • Patent number: D990891
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: July 4, 2023
    Inventor: Jie Chang
  • Patent number: D998270
    Type: Grant
    Filed: March 18, 2023
    Date of Patent: September 5, 2023
    Inventor: Jie Chang
  • Patent number: D998926
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: September 12, 2023
    Inventor: Jie Chang