Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: A voice command identification method for an electronic device having a microphone matrix is provided. The method includes: obtaining a plurality of sound signals from the microphone matrix; executing a voice purify operation on the sound signals to obtain a purified sound signal and identifying a target voice signal from the purified sound signal; calculating a compound speech feature data corresponding to the target voice signal through a compound speech recognition model; comparing the compound speech feature data with a plurality of reference speech feature data in the speech feature database, so as to determine a target command mapped to the target voice signal; and executing the target command.

Abstract: A method of manufacturing a semiconductor device includes forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged. The first and second transistor structures are separated by etching the source/drain structures.

Abstract: Systems and methods of updating firmware in a pair of wireless earbuds comprising at least a first earbud and a second earbud, may include wirelessly receiving at the first earbud a firmware update transmitted by a computing device; upgrading the first earbud, using the firmware update, during a first upgrade time interval; wirelessly receiving at the second earbud the firmware update; and upgrading the second earbud, using the firmware update, during a second upgrade time interval; wherein the first upgrade time interval and the second upgrade time interval at least partially overlap, resulting in a total firmware upgrade time interval for upgrading the first and the second earbuds being shorter than a sum of the first upgrade time interval and the second upgrade time interval.

Abstract: A semiconductor device includes an active area having source and drain regions and a channel region between the source and drain regions, an isolation structure surrounding the active area, and a gate structure over the channel region of the active area and over the isolation structure, wherein the isolation structure has a first portion under the gate structure and a second portion free from coverage by the gate structure, and a top of the first portion of the isolation structure is lower than a top of the second portion of the isolation structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

Abstract: A voice command identification method for an electronic device having a microphone matrix is provided. The method includes: obtaining a plurality of sound signals from the microphone matrix; executing a voice purify operation on the sound signals to obtain a purified sound signal and identifying a target voice signal from the purified sound signal; calculating a compound speech feature data corresponding to the target voice signal through a compound speech recognition model; comparing the compound speech feature data with a plurality of reference speech feature data in the speech feature database, so as to determine a target command mapped to the target voice signal; and executing the target command.

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

Abstract: A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.

Abstract: A method of manufacturing a semiconductor device includes forming a first transistor structure and a second transistor structure on a substrate, wherein source/drain structures of the first transistor structure and the second transistor structure are merged. The first and second transistor structures are separated by etching the source/drain structures.

Abstract: A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: Provided are uses of Bacteroides in preparation of a medicament. The medicament is for use in treatment or prevention of obesity and obesity-related diseases. Also provided are a pharmaceutical composition, a medicament, a food product, and an animal feed that comprise Bacteroides, uses thereof in treatment or prevention of obesity and obesity-related diseases, and a method for treatment or prevention of obesity and obesity-related diseases.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and a plurality of edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Abstract: A semiconductor device includes a substrate, an isolation structure, and a gate structure. The substrate has an active area. The isolation structure surrounds the active area of the substrate. The gate structure is across the active area of the substrate. The isolation structure has a first portion under the gate structure and a second portion adjacent to the gate structure. A top surface of the first portion of the isolation structure is lower than a top surface of the second portion of the isolation structure.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.