Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: A method for providing a logic synthesis of a pipeline circuit is disclosed. The method includes: providing a circuit design of the pipeline circuit, wherein the circuit design includes a first logic module as a current stage, and based on an operation of the first logic module, generating a first time marked graph (TMG) that corresponds to a plurality of behavioral phases of the first logic module, wherein the first TMG includes a plurality of vertexes and edges, wherein each vertex corresponds to one of the plurality of behavioral phases that occur in sequence and each edge is coupled between two respective vertexes thereby corresponding to a transition from one behavioral phase to another subsequently occurring behavioral phase.

Abstract: A power supply includes a housing receiving an electric motor, first and second fans, a generator, and a power device. The generator is concentrically mounted around the electric motor. When the electric motor is supplied with electricity from the power device and operates, a shaft of the electric motor drives the first fan to rotate, generating wind power close to the second fan. The second fan is rotated by the wind power in the housing and drives the second rotor and the second rotor seat to rotate. The first and second magnets create repulsive and attractive forces to provide inertia driving the second rotor seat, making the generator continuously supply electricity to the power device and the electric motor, thereby keeping the electric motor running to generate the wind power while the first fan continuously using the wind power to drive the second fan and the generator to generate electricity.

Abstract: A control board includes a storage module and a control module. The storage module includes a configured memory space and a non-configured memory space. The non-configured memory space further has at least one first storage unit, and each of the at least one first storage unit stores a first configuration document. The control module connected with the storage module switches to load the first configuration document under a control of a switch instruction by referring to a first mapping table, and bases on the first configuration document after the switching to allot a plurality of hard disk drives of a disk drive group connected with the control board to corresponding communication ports of the control module. Thus, access permission can be set in a physical layer of the expander board through at least one configuration document, and a certain number of storage units are allotted to store the configuration document.

Abstract: Provided are uses of Bacteroides in preparation of a medicament. The medicament is for use in treatment or prevention of obesity-related diseases. Also provided are a pharmaceutical composition, a medicament, a food product, and an animal feed that comprise Bacteroides, uses thereof in treatment or prevention of obesity-related diseases, and a method for treatment or prevention of obesity-related diseases.

Abstract: Provided are uses of Bacteroides in preparation of a medicament. The medicament is for use in treatment or prevention of obesity and obesity-related diseases. Also provided are a pharmaceutical composition, a medicament, a food product, and an animal feed that comprise Bacteroides, uses thereof in treatment or prevention of obesity and obesity-related diseases, and a method for treatment or prevention of obesity and obesity-related diseases.

Abstract: A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

Abstract: A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: A logic circuit includes first and second input, an output, an input acknowledgement node, an output acknowledgement node, a logic evaluation block, a pre-charging circuit, and a completion detection circuit. The logic evaluation block performs a logic evaluation of first and second input signals at the first and second inputs, and to output an output signal corresponding to the logic evaluation. The pre-charging circuit pre-charges the logic evaluation block in response to the first input signal and an acknowledgement signal at the input acknowledgement node. The completion detection circuit generates an acknowledgement signal at the output acknowledgement node in response to the second input signal and the output signal.

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract: A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The effective gate length or the effective channel width of the device is increased by lowering a top surface of an oxide isolation structure below the gate of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract: A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.

Abstract: The fluid philicity/phobicity adjustable surface structure is provided to hold a liquid. The surface structure includes a base and many small bumps located on the base. The small bumps are boxy in shape. Every small bump has at least one corner boundary, and the corner boundary is defined as a sudden change of the surface orientation. The gap between every two adjacent small bumps is smaller than the shortest cohesion diameter of the liquid. Additionally, the contact angle between the liquid and the hydrophilic hydrophobic adjustable surface structure is ? which satisfies the condition: ?*???(180??)+?*, where ?* is the contact angle between the base and the liquid, ? is the boundary edge angle of the small bump.

Abstract: A functional timing analysis method, executed in a computing device, comprises: step A: obtaining a circuit; step B: selecting a target delay time from a delay time set for a node in the circuit for verifying whether the target delay time is attainable by some input assignment; step C: generating a timed characteristic function associated with the selected target delay time for the node recursively from the timed characteristic functions associated with the corresponding delay times for its fanin nodes is generated as a target formula; step D: recursively translating the timed characteristic function into timed characteristic function clauses of the target formula by using an implication operator; step E: checking whether the target formula is satisfied by using a Boolean satisfiability solver; and step F: if the target formula is satisfied, the selected target delay time is attainable by some input assignment to the circuit.

Abstract: A circuit for preheating filaments may include: a transistor; a first winding, one terminal of which being electrically connected with a collector of the transistor, and the other terminal being connected to an input of a power source; a second winding, one terminal of which being electrically connected with an emitter of the transistor, the other terminal being electrically connected with a base of the transistor, and the second winding being coupled with the first winding in a self-excitation mode; one or more load windings respectively connected with the filaments in series, and each of which being coupled with the first winding in a flyback mode; and a delay switch, configured to change into an on state from an off state when a trigger signal with a predetermined delay is received, so as to turn off the transistor.

Abstract: The fluid philicity/phobicity adjustable surface structure is provided to hold a liquid. The surface structure includes a base and many small bumps located on the base. The small bumps are boxy in shape. Every small bump has at least one corner boundary, and the corner boundary is defined as a sudden change of the surface orientation. The gap between every two adjacent small bumps is smaller than the shortest cohesion diameter of the liquid. Additionally, the contact angle between the liquid and the hydrophilic/hydrophobic adjustable surface structure is ? which satisfies the condition: ?*???(180??)+?*, where ?* is the contact angle between the base and the liquid, ? is the boundary edge angle of the small bump. In detail, the boundary edge angle ? is the solid edge angle subtended by the two surfaces forming the edge, and ? is smaller than 180 degrees.