Abstract: A method for controlling flows of a logical link layer in a near field communication (NFC) software stack includes steps of: arranging a Send Window and a Receive Window in the logical link layer for controlling flows of transmitted data frames; adjusting the size of the Send Window and the size of the Receive Window according to a transfer rate determined based on upper-layer application, communication delay time determined based on channel quality, and the size of a data frame; and controlling flows of the output terminal according to the size of the Send Window, and controlling flows of the input terminal according to the size of the Receive Window.

Abstract: A power conversion system includes at least one multi-level power converter and a controller coupled to the at least one multi-level power converter. The controller includes a first CMV injection module and a second CMV injection module. The first CMV injection module generates a first CMV signal for modifying at least one voltage command to achieve a first function in association with operation of the power conversion system. The second CMV injection module generates a second CMV signal based at least in part on a local limit either for modifying the at least one voltage command or for further modifying the at least one modified voltage command to achieve a second function in association with operation of the power conversion system.

Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

Abstract: In an integrated-circuit image sensor, binary sample values are read out from an array of pixels after successive sampling intervals that collectively span an image exposure interval and include at least two sampling intervals of unequal duration. Each pixel of the array is conditionally reset after each of the successive sampling intervals according to whether the pixel yields a binary sample in a first state or a second state.

Abstract: Methods and systems for increasing the effective dynamic range of an image sensor are disclosed. Each pixel in the sensor is exposed for a respective first exposure time. Each pixel's response to the respective first exposure is measured and compared to threshold values. Based on the pixel's response to the respective first exposure time, an optimal exposure is calculated for each pixel. The optimal exposure time is applied to each pixel by utilizing row-enabled and column-enabled signals at each pixel within the sensor.

Abstract: Prostamide-containing biodegradable intraocular implants, prostamide compounds, prostamide-containing pharmaceutical compositions, and methods for making and using such implants and compositions for the immediate and sustained reduction of intraocular pressure and treatment of glaucoma in an eye of a patient are described.

Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

Abstract: The present invention is directed to preservative-free solutions of bimatoprost and timolol for lowering intra-ocular pressure and treatment of glaucoma.

Abstract: A grid-side transformerless power conversion system configured to perform power conversion between a power grid and a load, the transformerless power conversion system includes a first converter, a first filter, and a second converter. The first converter is configured to convert first AC power provided from the power grid into DC power. The first converter includes a first converter module and a second converter module coupled to the first converter module to form a nested neutral point piloted topology. The first filter is coupled between the power grid and the first converter. The second converter is coupled to the first converter. The second converter is configured to convert the DC power into second AC power and provide the second AC power to the load.

Abstract: A converter includes a first converter module and a second converter module coupled to the first converter module in a nested manner. Each of the first converter module and the second converter module includes a plurality of switch units. When the converter is operated to perform power conversion, at least two of the plurality of switch units is configured to be switched both in a complementary pattern and a non-complementary pattern.

Abstract: A power converter is presented. The power converter includes at least one leg operatively coupled between a first bus and a second bus and includes a first string including a plurality of non-controllable semiconductor switches, a first node, a second node, and a third node, where the first node is coupled to a third bus, one or more second strings, where each of the one or more second strings includes at least one fully controllable semiconductor switch, and where one of the second strings is coupled between the first node and the third bus and another second string is coupled between the second node and the third node, and one or more third strings, where each of the one or more third strings includes at least one energy storage device and is coupled to the first string, the one or more second strings, or a combination thereof.

Abstract: A multi-phase partial response equalizer is disclosed. The equalizer includes receiver circuitry to receive a data symbol over N bit intervals and to generate N sets of samples in response to N clock signals having different phases. A first storage stage is provided, including storage elements to store the sets of samples during a common clock interval. First and second selection circuits are respectively coupled to an input and an output of the first storage stage. An output storage stage is coupled to the second selection circuit to store an output sample. The first and second selection circuits, over multiple clock intervals, cooperatively select the output sample from one of the sets of samples based on a most recent previous output sample.

Abstract: An electromagnetic shielding structure includes a first shielding material disposed at a first location with respect to at least one radiation source and a second shielding material attached with the first shielding material by fastening means. The second shielding material is disposed at a second location with respect to the at least one electromagnetic radiation source so as to define a predetermined gap between the first shielding material and the second shielding material. The first shielding material shields at least part of first frequency electromagnetic radiations generated from the at least one electromagnetic radiation source and penetrating through the second shielding material and the predetermined gap. The second shielding material shields at least part of second frequency electromagnetic radiations generated from the at least one electromagnetic radiation source.

Abstract: A split-counter architecture is implemented within an image sensor system. A first counter within an image sensor region counts image data from pixel regions within the image sensor region, and outputs the most significant bits of the image data to a second counter external to the image sensor region, reducing the bandwidth required between the image sensor region and the second counter, and reducing the size of the counters within the image sensor region.

Abstract: In a method for outputting dimension data using a computing device, a dimension file is read and searched for at least one dimension keyword. If there is the at least one dimension keyword in the dimension file, dimension data from the dimension file is extracted and stored as one or more structure variables into a structure array. Each of the one or more structure variables is added into a dimension field of a preset general list. Each dimension field in the preset general list is output into an output report according an output position of each dimension field, and the output report is displayed on a display screen.

Abstract: A method of assembling a testing apparatus for a full-power converter assembly includes coupling an electric power supply apparatus to an electric power grid. The method also includes coupling a direct current (DC) generation apparatus to the electric power supply apparatus. The method further includes coupling an electric power grid simulation device to the DC generation apparatus. The method also includes coupling a full-power converter assembly test connection to the electric power grid simulation device.

Abstract: A high voltage direct current system is presented. The system includes at least three high voltage direct current terminals. Furthermore, the system include at least two transmission lines configured to operatively couple the at least three high voltage direct current terminals. Moreover, the system includes a power flow control device operatively coupled to at least one end of one or more of the at least two transmission lines and at least one of a local grid and another power flow control device. Methods to perform the method for power flow control are also presented.

Abstract: One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus enabling those pins to be used as C/A pins when the PHY is connected to some memory types, and as DQ pins when the PHY is connected to other memory types.

Abstract: A control system for a multilevel converter includes a differential mode current regulator, a neutral point (NP) controller and a PWM controller for generating switching pulses for the multilevel converter. The differential mode current regulator generates reference voltage command signals based on a difference between reference current command signals and actual current command signals, and the NP controller determines a modified neutral point current signal in response to a DC link voltage unbalance. The NP controller utilizes the modified neutral point current signal to generate a common mode reference voltage signal. The switching pulses are generated by the PWM controller based on the reference voltage command signals and the common mode reference voltage signal.

Abstract: A power inverter system includes a DC to AC inverter configured to convert DC voltage from a DC power source to AC voltage. A DC link couples the DC power source and the inverter. An inverter pre-charger operates to pre-charge the inverter to achieve a desired DC link voltage prior to connecting the power inverter system to an AC power grid. A phased lock loop synchronizes the pre-charged inverter to the AC power grid prior to connecting the power inverter system to the AC power grid. The pre-charged inverter regulates the DC link voltage to about the minimum voltage level that allows control of AC grid currents via the inverter subsequent to connecting the power inverter system to the AC grid. The inverter operates in a maximum power point tracking control mode only subsequent to a first voltage transient caused by connecting the DC power source to energize the power inverter system.