Abstract: A method used to control the operation of a converting device such that it can provide multi-level output voltage for loads. This method comprises at least the steps of: determine whether the load which the converter is providing electricity for is operating under the first condition or the second condition; generate the first pulse signal after determining that this load is operating under the first condition, select at least one of at least three different current paths, such that when the converter is selecting any of the current paths, it can provide output voltage at the same level; as well as generate the second pulse signal after determining that this load is operating under the second condition, such that the converter can perform the regular energy conversion operations.

Abstract: Prostamide-containing biodegradable intraocular implants, prostamide compounds, prostamide-containing pharmaceutical compositions, and methods for making and using such implants and compositions for the immediate and sustained reduction of intraocular pressure and treatment of glaucoma in an eye of a patient are described.

Abstract: A method of manufacturing a semiconductor device includes fabricating a transistor, surrounding a gate of the transistor with a spacer, and applying an oxidation operation to a conductive item, e.g., a residue from the fabrication of the gate of the transistor, that extends through the spacer. As such, the occurrence of leak paths in the semiconductor device is reduced.

Abstract: Embodiments disclosed herein are directed to fixed compositions comprising brimonidine and timolol for lowering intraocular pressure and treating glaucoma.

Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.

Abstract: Prostamide-containing biodegradable intraocular implants, prostamide compounds, prostamide-containing pharmaceutical compositions, and methods for making and using such implants and compositions for the immediate and sustained reduction of intraocular pressure and treatment of glaucoma in an eye of a patient are described.

Abstract: An exemplary power conversion system includes a power conversion device and a control system. The power conversion device converts electrical power from one form to another. The power conversion device includes at least one switching element capable of being turned off to block an electrical current flowing through the at least one switching element. The control system is electrically coupled to the power conversion device for monitoring an electrical current flowing through the at least one switching element and for monitoring at least one parameter in association with the operation of the power conversion system. The control system further generates an over-current threshold value that is variable with respect to at least one monitored parameter.

Abstract: Provided are a series of BTK inhibitors, and specifically disclosed are a compound, pharmaceutically acceptable salt thereof, tautomer thereof or prodrug thereof represented by formula (I), (II), (III) or (IV).

Abstract: A system, a switch assembly and an associated method. The system includes a number of switch assemblies, each including a switch module, isolation circuits, a detection unit, and a drive unit. The switch module includes power switch devices connected in parallel. The switch modules are connected in series. The isolation circuits each are connected in series to a gate terminal of at least one corresponding power switch device of the power switch devices. Each isolation circuit includes a capacitor or a controllable switch. The detection unit detects faults in at least one of the power switch devices. The drive unit is coupled to the switch module via the isolation circuits for driving the power switch devices of the corresponding switch module, and when the fault is detected, the drive unit is for turning on the power switch devices parallel connected to the at least one of faulty power switch devices.

Abstract: A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void.

Abstract: The present invention is directed to preservative-free solutions of bimatoprost and timolol for lowering intra-ocular pressure and treatment of glaucoma.

Abstract: A power conversion system includes at least one multi-level power converter and a controller coupled to the at least one multi-level power converter. The controller includes a first CMV injection module and a second CMV injection module. The first CMV injection module generates a first CMV signal for modifying at least one voltage command to achieve a first function in association with operation of the power conversion system. The second CMV injection module generates a second CMV signal based at least in part on a three-level CMV limit either for modifying the at least one voltage command or for further modifying the at least one modified voltage command to achieve a second function in association with operation of the power conversion system.

Abstract: Stacked chip imaging system comprising pixel array partitioned into pixel sub-arrays (PSAs) disposed in first semiconductor die and ADC circuitry including ADC circuits disposed in second semiconductor die. Each PSA is arranged into pixel groups. Each pixel group generates pixel data signals. Pixel array captures image data of first frame with first exposure time, second frame with second exposure time, third frame with third exposure time, and fourth frame with fourth exposure time. First, second, third and fourth exposure times are different. At least one of the pixel groups in each of the pixel sub-arrays is coupled to a different ADC circuit from pixels groups remaining in each of the pixel sub-arrays. ADC circuitry acquires the pixel data signals. For each frame, ADC circuits converts pixel data signal received from pixel groups respectively coupled thereto from analog to digital to generate ADC outputs. Other embodiments are also described.

Abstract: The present disclosure relates to the alignment of moieties (e.g., nanoparticles and/or nanowires) into prescribed architectures on two- and/or three-dimensional substrates (e.g., nucleic acid nanostructures/crystals). The present disclosure also relates to a nucleic acid (e.g., DNA) lithography method that includes, in some embodiments, adsorbing a bare nucleic acid nano-structure onto a surface of a substrate, and etching the surface of the substrate containing the bare nucleic acid nanostructure, thereby producing a patterned substrate.

Abstract: Stacked chip imaging system comprising pixel array partitioned into pixel sub-arrays (PSAs) disposed in first semiconductor die and ADC circuitry including ADC circuits disposed in second semiconductor die. Each PSA is arranged into pixel groups. Each pixel group generates pixel data signals. Pixel array captures image data of first frame with first exposure time, second frame with second exposure time, third frame with third exposure time, and fourth frame with fourth exposure time. First, second, third and fourth exposure times are different. At least one of the pixel groups in each of the pixel sub-arrays is coupled to a different ADC circuit from pixels groups remaining in each of the pixel sub-arrays. ADC circuitry acquires the pixel data signals. For each frame, ADC circuits converts pixel data signal received from pixel groups respectively coupled thereto from analog to digital to generate ADC outputs. Other embodiments are also described.

Abstract: Disclosed are a method, an electronic device and a system for playing multiple channels of video data. The method includes: obtaining a play request for playing multiple channels of video data from a client, wherein identification information of a terminal device and identification information corresponding to the multiple channels of video data are carried in the play request; according to the identification information of the terminal device, determining the number of video layers corresponding to the terminal device; if it is determined that the number of the multiple channels of video data is greater than the number of video layers, according to the identification information corresponding to the multiple channels of video data, obtaining the same number of channels of video data as the number of video layers and picture data corresponding to remaining channels of video data, and sending the obtained data to the client. The picture data is picture representation of corresponding video data.

Abstract: A method of detecting light-emitting diode (LED) light starts with a control circuitry generating a shutter signal that is transmitted to a pixel array to control image acquisition by the pixel array and to establish a set exposure time. The readout circuitry may then read out the image data from the pixel array that includes reading out the image data from a plurality of successive and overlapped frames having the set exposure time. The set exposure time may be the same for each of the frames. The successive and overlapped frames may be interlaced frames. Other embodiments are also described.

Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.

Abstract: A system and method for high dynamic range (HDR) imaging includes writing a first, second, and third sub-frame to a memory at a first, second, and third readout time, respectively, the first, second, and third sub-frame being generated by a same first sub-array of the array of image pixels. Subsequent to the third readout time, the first, second, and third sub-frames are sent to an image signal processor. Also subsequent to the third readout time, a fourth sub-frame is sent to the image sensor. The fourth sub-frame is generated by the same first sub-array of the array of image pixels. The fourth sub-frame bypasses the memory by being sent from an analog-to-digital converter to the image signal processor without being written to the memory.

Abstract: A floorplan-optimized stacked image sensor and a method for designing the sensor are disclosed. A sensor layer includes multiple PSAs partitioned into PSA groups. A circuit layer includes multiple analog-to-digital converters each communicatively coupled to a different PSA. Each analog-to-digital converter (ADC) is semi-aligned to the PSA group associated with the PSA to which it is communicatively coupled. The floorplan of ADCs maximizes contiguous global-based space on the circuit layer uninterrupted by an ADC. The resulting circuit layer floorplan has one or more global-based spaces interleaved with one or more local-based spaces containing ADCs.