Patents by Inventor Jie Wei

Jie Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110838
    Abstract: A graphene heating chip includes a substrate, an insulating layer, a graphene film, and a plurality of electrodes. The substrate has two opposite a first surface and a second surface, and the substrate defines a through hole. The insulating layer is suspended on the substrate. The insulating layer covering the through hole and not in direct contact with the first surface is defined as a window, and a plurality of grooves are formed on the window. The graphene film covers the window, and the graphene film includes a first graphene film portion and a second graphene film portion, and the first graphene film portion and the second graphene film portion are spaced apart from each other. The plurality of electrodes are located on the surface of the insulating layer away from the substrate. The present application also provides a method for calibrating a temperature of the graphene heating chip.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 4, 2024
    Inventors: JIE ZHAO, LIANG LIANG, YANG WEI, QUN-QING LI, SHOU-SHAN FAN
  • Publication number: 20240114597
    Abstract: A graphene heating chip includes a substrate, an insulating layer, a graphene film, and a plurality of electrodes. The substrate has two opposite a first surface and a second surface, and the substrate defines a through hole. The insulating layer is suspended on the substrate. The insulating layer covering the through hole and not in direct contact with the first surface is defined as a window, and a plurality of grooves are formed on the window. The graphene film covers the window, and the graphene film includes a first graphene film portion and a second graphene film portion, and the first graphene film portion and the second graphene film portion are spaced apart from each other. The plurality of electrodes are located on the surface of the insulating layer away from the substrate. The present application also provides a method for making the graphene heating chip.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 4, 2024
    Inventors: LIANG LIANG, JIE ZHAO, YANG WEI, QUN-QING LI, SHOU-SHAN FAN
  • Patent number: 11942454
    Abstract: A package includes a first die, a second die, and an encapsulant. The first die has a first interconnection structure, and the first interconnection structure includes a first capacitor embedded therein. The second die has a second interconnection structure, and the second interconnection structure includes a second capacitor embedded therein. The first interconnection structure faces the second interconnection structure. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11942112
    Abstract: A method for starting hard disks, applied in an electronic device, the method includes: starting a storage in the electronic device, and the storage comprising hard disks and a backplane extension chip; sending preset request signals by the hard disks to the backplane extension chip; verifying a number of the hard disks by the backplane expansion chip according to the request signals; when the number of the hard disks is verified successfully, performing type verification on the hard disks by the backplane expansion chip; and sending a start signal by the backplane expansion chip to the target hard disks having a successful type verification according to a preset start sequence and a preset number of the hard disks, to start the target hard disks.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: March 26, 2024
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventors: Wei Wei, Jie Yuan
  • Publication number: 20240098953
    Abstract: This application discloses electromagnetic energy mitigation assemblies and automotive vehicle components comprising the electromagnetic energy mitigation assemblies. An electromagnetic energy mitigation assembly includes a first electrically conductive layer and a second electrically conductive layer. First and second permalloy layers are along respective first and second opposite sides of the first electrically conductive layer. Third and fourth permalloy layers are along respective third and fourth opposite sides of the second electrically conductive layer. An electromagnetic noise suppression layer is sandwiched between the second and third permalloy layers. An automotive vehicle component includes an electromagnetic energy mitigation assembly configured to be positioned relative to one or more batteries of an automotive vehicle for providing electromagnetic shielding for the one or more batteries. The electromagnetic energy mitigation assembly includes a first electrically conductive layer.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 21, 2024
    Inventors: Tsang-I TSAI, Yunxi SHE, Dong-Xiang LI, Jie-Sheng CHEN, Min-Wei HSU
  • Publication number: 20240096706
    Abstract: The present disclosure provides a method of forming a semiconductor device. The method includes: forming an interconnect structure over a substrate; forming a first gate structure and a second gate structure in a first layer of the interconnect structure; forming a first metal oxide layer and a second metal oxide layer in a second layer of the interconnect structure over the first gate structure and the second gate structure, respectively; forming an implant mask over the first metal oxide layer and the second metal oxide layer, the implant mask having different thicknesses corresponding to the first metal oxide layer and the second oxide layer; and performing an implantation operation on the first metal oxide layer and the second metal oxide layer.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Inventors: YEN-CHUNG HO, YONG-JIE WU, HUI-HSIEN WEI
  • Publication number: 20240091427
    Abstract: The present disclosure discloses an electric nasal aspirator with anti-blocking and cleaning functions, including a housing assembly, provided with an exhaust hole and an air suction column penetrating through the housing assembly; a circuit board, fixedly arranged in the housing assembly; a collection cup assembly, detachably arranged on the housing assembly, wherein the collection cup assembly includes an outer cover, a collection cup, and a suction nozzle; the outer cover is detachably hermetically connected to the housing assembly; the collection cup includes a connecting column and a collection chamber; the connecting column is hollowly tubular and detachably arranged on the air suction column.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventor: Jun Jie WEI
  • Publication number: 20240088028
    Abstract: A semiconductor package includes a die and a plurality of conductive patterns. The die includes a device. The conductive patterns are disposed over the device, wherein the conductive patterns are electrically connected to one another to form a first coil and a second coil surrounding the first coil.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20240088122
    Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Publication number: 20240088104
    Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
  • Patent number: 11927608
    Abstract: The present disclosure relates to an AC/DC closed-loop current sensor, including a magnetism gathering iron core, a TMR chip, a signal processing circuit, a signal generator, and a feedback coil. The TMR chip is arranged at an air gap of the magnetism gathering iron core and connected to the signal processing circuit. The signal processing circuit is connected to the signal generator. The feedback coil is wound around the magnetism gathering iron core and connected to the signal generator. The signal processing circuit is configured to select from the induced signal of the TMR chip and make an amplification to obtain a current signal component and send the current signal component to the signal generator. The signal generator is configured to adjust a current output to the feedback coil based on the current signal component, and output a measurement result of the selected current signal component.
    Type: Grant
    Filed: September 18, 2023
    Date of Patent: March 12, 2024
    Assignee: DIGITAL GRID RES. INST., CHINA SOUTHERN PWR. GRID
    Inventors: Peng Li, Qiancheng Lv, Bing Tian, Xiaopeng Fan, Zhong Liu, Zhiming Wang, Renze Chen, Jie Wei, Xu Yin, Zejie Tan, Zhenheng Xu, Senjing Yao, Licheng Li, Yuehuan Lin, Shengrong Liu, Bofeng Luo, Jiaming Zhang
  • Publication number: 20240076444
    Abstract: The present invention relates to a polybutylene terephthalate composition, and an article derived from the polybutylene terephthalate composition comprising as component (A) polybutylene terephthalate (PBT) resin, as component (B) vinyl aromatic-based polymer comprising units which are derived from vinyl aromatic monomers, and as component (C) reinforcement agent.
    Type: Application
    Filed: October 13, 2020
    Publication date: March 7, 2024
    Inventors: Chao Liu, Qiong Jie Han, Roland Helmut Kraemer, Zhen Ke Wei
  • Publication number: 20240079324
    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie CHEN, Ying-Ju CHEN, Chen-Hua YU, Der-Chyang YEH, Hsien-Wei CHEN
  • Publication number: 20240079198
    Abstract: The present invention provides an emitter made of a hafnium carbide (HfC) single crystal that stably emits electrons with high efficiency, a method for manufacturing the emitter, and an electron gun and an electronic device using the emitter. An emitter according to an embodiment of the present invention is an emitter including a nanowire, in which the nanowire is made of the hafnium carbide (HfC) single crystal, at least an end of the nanowire through which electrons are to be emitted is coated with hafnium oxycarbide (HfC1?xOx: 0<x?0.5), and a field electron emission pattern of the end obtained by a field emission microscope (FEM) is a single spot.
    Type: Application
    Filed: June 29, 2020
    Publication date: March 7, 2024
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jie TANG, Shuai TANG, Ta-Wei CHIU, Wataru HAYAMI, Luchang QIN
  • Publication number: 20240070043
    Abstract: A method for detecting performance of a number of hard disks working under various operating systems, comprising: collecting of performance parameter of hard disks in several pre-determined systems, storing the parameters in a uniform format to obtain unified data; analyzing the unified data to obtain feature parameters of the hard disk; comparing the feature parameters and preset name string to obtain performance data of the hard disk; classifying the hard disk and establishing a performance database by the performance data of the hard disks of different kinds; presenting the data in the performance database with a preset visual tool, the data is regarded detecting results of the hard disks. Performance data from a plurality of systems can thus be presented by the visual tool running across platforms, which improves the scope and immediacy of detection. An apparatus, an electrical device, and a storage medium are also disclosed.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 29, 2024
    Inventors: WEI WEI, JIE YUAN
  • Publication number: 20240070224
    Abstract: The present disclosure provides a method for identifying modal parameters of engineering structures based on fast stochastic subspace identification, and relates to the field of structural modal parameters identification. The method includes the following steps: collecting responses; obtaining a unitary matrix by performing random projection on and QR decomposition of a matrix; obtaining a small matrix by projecting a Toeplitz matrix onto the unitary matrix; obtaining U, S, V matrices respectively by performing singular value decomposition of the small matrix; performing eigenvalue decomposition; and determining an order interval. According to the present disclosure, the small matrix is obtained through performing random projection on and QR decomposition of the traditional Toeplitz matrix, the dimensionality of the matrix by singular value decomposition is reduced and the computational efficiency of the matrix is improved.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 29, 2024
    Inventors: Maosen Cao, Qingyang Wei, Jie Wang, Yufeng Zhang, Xiangdong Qian, Dragoslav Sumarac, Emil Manoach, Shuai Li
  • Patent number: 11915920
    Abstract: The present invention provides a simpler method for sharpening a tip of an emitter. In addition, the present invention provides an emitter including a nanoneedle made of a single crystal material, an emitter including a nanowire made of a single crystal material such as hafnium carbide (HfC), both of which stably emit electrons with high efficiency, and an electron gun and an electronic device using any one of these emitters. A method for manufacturing the emitter according to an embodiment of the present invention comprises processing a single crystal material in a vacuum using a focused ion beam to form an end of the single crystal material, through which electrons are to be emitted, into a tapered shape, wherein the processing is performed in an environment in which a periphery of the single crystal material fixed to a support is opened.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 27, 2024
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jie Tang, Shuai Tang, Ta-Wei Chiu, Tadakatsu Ohkubo, Jun Uzuhashi, Kazuhiro Hono, Luchang Qin
  • Patent number: 11906552
    Abstract: The present disclosure relates to a voltage measuring method, a computer device and a storage medium. The method includes: determining, by a voltage measuring device when the voltage measuring device is electrically coupled to a three-phase conductor through a voltage dividing capacitor in the voltage measuring device, a current measured voltage, the measured voltage being determined by measuring a voltage of the voltage dividing capacitor in the voltage measuring device; adjusting the coupling capacitances, and determining, by the voltage measuring device after the adjustment of the coupling capacitances, a current measured voltage; and determining, based on the measured voltage by the voltage measuring device before the adjustment of the coupling capacitances and the measured voltage by the voltage measuring device after the adjustment of the coupling capacitances, a voltage of a phase conductor of the three-phase conductor to be measured.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: February 20, 2024
    Assignee: DIGITAL GRID RES. INST, CHINA SOUTHERN POWER GRID
    Inventors: Peng Li, Bing Tian, Zhong Liu, Bofeng Luo, Zhiming Wang, Licheng Li, Xiaopeng Fan, Senjing Yao, Qiancheng Lv, Zhenheng Xu, Renze Chen, Yuehuan Lin, Xu Yin, Jiaming Zhang, Jie Wei, Zejie Tan
  • Publication number: 20230393073
    Abstract: A test system comprising: a carrier disc configured to carry a target sample; a light source module configured for emitting at least two types of reference light with different wavelengths; a light guiding module located on an emitting path of the reference light and configured for guiding the reference light to the target sample and for receiving and guiding at least two types of detection light with different wavelengths, the detection light being generated by the target sample according to the reference light; and a detection module configured for receiving the detection light and obtaining biochemical information of the target sample according to the detection light.
    Type: Application
    Filed: November 4, 2020
    Publication date: December 7, 2023
    Inventors: YI HUANG, HEMING JIANG, JIE WEI, SONG-LIN LI
  • Publication number: 20230388238
    Abstract: A method of reducing network traffic includes blocking, at a mobile device, a first channel to reduce network signaling in a network and to reduce battery consumption. The first channel includes a non-common channel. The method includes offloading application traffic of an application onto a second channel. The second channel may include a common channel. The method may include monitoring the application traffic of the application over the second channel, unblocking the first channel based on the monitored application traffic so that the application can perform an action, and re-blocking the first channel after the action has been completed. The method may include unblocking the first channel when user activity is detected, wherein the user activity includes whether the mobile device is being interacted with.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 30, 2023
    Inventors: Rami Alisawi, Ari Backholm, Huajie Hu, Alexandr Seleznyov, Jie Wei, Sungwook Yoon