Abstract: A booster unit (40) and a reverse osmosis filtration system (100). The booster unit (40) includes: a booster pump (45), wherein the pump fluid outlet (4512) is connected to a fluid outlet port (P2); and a housing. The housing includes an outer housing (41) and an inner housing (42) at least partially mounted in the outer housing (41). The booster pump (45) is provided in an inner cavity of the inner housing (42). A fluid channel is formed between the outer housing (41) and the inner housing (42); a fluid inlet of the fluid channel is connected to a fluid inlet port (P1) of the booster unit (40), and a fluid outlet of the fluid channel is connected to a pump fluid inlet (4511) of the booster pump (45). The reverse osmosis filtration system (100) comprises the booster unit (40).

Abstract: Systems and methods for navigation and identification for endoscopic kidney surgery may include generating a map of an internal space of a patient's collecting system, including segmentation preoperative CT scans, using localization and three-dimensional reconstruction techniques on endoscopic video to create a point cloud, and registering the point cloud to the segmented CT scans. The systems and methods may include tracking a tip of the endoscope during the endoscopic kidney surgery using localization and three-dimensional reconstruction techniques. The systems and methods may include identifying and tracking kidney stones during the endoscopic kidney surgery using computational models.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: The present invention relates to Sitagliptin intermediate and preparation method and use thereof. The method comprises reacting compound of formula (II) and trifluorobromobenzene with a Grignard reagent by a Grignard reaction to obtain a compound of formula (I). Compound of formula (I) is a new intermediate compound for the synthesis of Sitagliptin. Compound of formula (I) can be easily used for preparing another important intermediate compound of formula (V) for the synthesis of Sitagliptin.

Abstract: The present invention relates to Sitagliptin intermediate and preparation method and use thereof. The method comprises reacting compound of formula (II) and trifluorobromobenzene with a Grignard reagent by a Grignard reaction to obtain a compound of formula (I). Compound of formula (I) is a new intermediate compound for the synthesis of Sitagliptin. Compound of formula (I) can be easily used for preparing another important intermediate compound of formula (V) for the synthesis of Sitagliptin.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: A voltage protection circuit includes a first voltage dividing circuit, a second voltage dividing circuit, a transistor and a switching power supply integrated circuit. The first resistor includes a first resistor and a second resistor. The second voltage dividing circuit includes a third resistor and a fourth resistor. The transistor with a base connected to a common end of the first resistor and the second resistor, a collector connected to a common end of the third resistor and the fourth resistor, an emitter connected to ground. The switching power supply integrated circuit includes an input pin, an enable pin and an output pin.