Abstract: A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.

Abstract: A source-network-load-storage coordination dispatching method in a background of a coupling of renewable energy sources, including: taking an expectation of a minimum grid operating cost in a dispatching cycle as an objective function; generating an approximate value function of an output of a set for generating electricity from renewable energy sources and a user load, and constructing a source-network-load-storage coordination dispatching model with combination of the objective function; obtaining forecast data of the output of a set for generating electricity from renewable energy sources and the user load, and inputting the forecast data into the dispatching model for solving; performing iterative updating on the approximate value function, importing the approximate value function after the iterative updating into the dispatching model for iterative solving, and terminating an iterative process until a solving result satisfies a preset convergence condition; and using a solving result of a last iteration

Abstract: Disclosed are a photovoltaic energy storage offline coordination system and method based on demand management. The system includes a photovoltaic generator set, an inverter, a dispatch and control device for charge-discharge, a load monitor, a first and second energy storage device, and a remote console. The photovoltaic generator set is electrically connected to the dispatch and control device for charge-discharge via the inverter; the first energy storage device is connected to a load-side power supply bus via a first dispatch and control unit; the second energy storage device is connected to the load-side power supply bus via a third dispatch and control unit; a second dispatch and control unit is connected to the load-side power supply bus; the load monitor is provided at the load-side power supply bus, and configured to monitor a load of the load-side.

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

Abstract: Embodiments of this application provide a method and system for adjusting a memory, and a semiconductor device. The method for adjusting a memory includes: acquiring a mapping relationship among a temperature of a transistor, a substrate bias voltage of a sense amplification transistor in a sense amplifier, and an actual data writing time of the memory; acquiring a current temperature of the transistor; and adjusting the substrate bias voltage on the basis of the current temperature and the mapping relationship, such that an actual data writing time corresponding to an adjusted substrate bias voltage is within a preset writing time.

Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.

Abstract: A read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a preset memory space if an error occurs in the data to be read out, and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule.

Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

Abstract: Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.

Abstract: A method that includes measuring vibration levels in a semiconductor manufacturing apparatus, determining one or more sections of the semiconductor manufacturing apparatus that vibrate at levels greater than a predetermined vibration level, and reducing the vibration levels in the one or more sections to be at or within the predetermined vibration level by coupling one or more weights to an external surface of the semiconductor manufacturing apparatus in the one or more sections.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: The present invention relates to Sitagliptin intermediate and preparation method and use thereof. The method comprises reacting compound of formula (II) and trifluorobromobenzene with a Grignard reagent by a Grignard reaction to obtain a compound of formula (I). Compound of formula (I) is a new intermediate compound for the synthesis of Sitagliptin. Compound of formula (I) can be easily used for preparing another important intermediate compound of formula (V) for the synthesis of Sitagliptin.

Abstract: The present invention relates to Sitagliptin intermediate and preparation method and use thereof. The method comprises reacting compound of formula (II) and trifluorobromobenzene with a Grignard reagent by a Grignard reaction to obtain a compound of formula (I). Compound of formula (I) is a new intermediate compound for the synthesis of Sitagliptin. Compound of formula (I) can be easily used for preparing another important intermediate compound of formula (V) for the synthesis of Sitagliptin.

Abstract: The invention relates to a novel process, novel process steps and novel intermediates useful in the synthesis of pharmaceutically active compounds, in particular neutral endopeptidase (NEP) inhibitors.

Abstract: A voltage protection circuit includes a first voltage dividing circuit, a second voltage dividing circuit, a transistor and a switching power supply integrated circuit. The first resistor includes a first resistor and a second resistor. The second voltage dividing circuit includes a third resistor and a fourth resistor. The transistor with a base connected to a common end of the first resistor and the second resistor, a collector connected to a common end of the third resistor and the fourth resistor, an emitter connected to ground. The switching power supply integrated circuit includes an input pin, an enable pin and an output pin.