Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: An image scanning apparatus includes a controller configured to perform a light quantity adjustment determining process to determine whether a detection light quantity needs to be adjusted, based on adjustment determination values, in a black-white detectable position, a light quantity adjusting process to adjust the detection light quantity to maximize an adjustment difference value between a gradation value generated by scanning a white portion of a reference member and a gradation value generated by scanning a black portion of the reference member, a threshold calculating process to calculate a detection threshold based on a black value and a white value, and a reference position detecting process to detect a reference position by comparing, with the detection threshold, gradation values generated by scanning the reference member while illuminating the reference member with the detection light quantity.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: Communication between one communication bus having one set of characteristics and another communication bus having another set of characteristics is facilitated by a bridge coupling the two communication buses. The bridge includes a scoreboard to manage data communicated between the buses. In one particular example, the one communication bus is a Processor Local Bus (PLB6) and the other communication bus is an Application Specific Integrated Chip (ASIC) Interconnect Bus (AIB).

Abstract: A probe clip allows easy and accurate placement of a probe clip onto a coordinate measuring machine (“CMM”). Moreover various probe clips are configured to movably and adjustably secure an optical probe to the CMM. To that end, the probe clip may have a probe seat, for holding the probe, movably coupled to a clamp segment by an adjustable joint. The clamp segment movably couples the probe seat to a probe platform on the CMM.

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

Abstract: A method for recognizing a thief zone in an oil pool, a computer apparatus and a computer readable storage medium, wherein, the method comprises: calculating a yield contribution value per unit thickness for single-reservoir stratum and a relative contribution coefficient of individual reservoir stratum in oil pool production logging, the relative contribution coefficient being a ratio of the yield contribution value per unit thickness for single-reservoir stratum to a yield per unit thickness for the whole reservoir stratum interval; determining a smallest yield contribution value per unit thickness for single-reservoir stratum and a smallest relative contribution coefficient from the yield contribution values per unit thickness for single-reservoir stratum and the relative contribution coefficients in the oil pool production logging, according to the characteristics of different oil pools; calculating the yield contribution value per unit thickness for single-reservoir stratum and the relative contribution

Abstract: Embodiments of the present disclosure relate to a CAPTCHA generation method. According to the method, a request for accessing a resource is received from a handheld touch screen device. A default virtual keyboard type is received from the handheld touch screen device. In response to the request, a CAPTCHA is generated based on the default virtual keyboard type. The CAPTCHA is sent to the handheld touch screen device.

Abstract: A method of forming a hybrid physically and chemically cross-linked double-network hydrogel with highly recoverable and mechanical properties in a single-pot synthesis is provided. The method comprises the steps of combining the hydrogel precursor reactants into a single pot. The hydrogel precursor reactants include water; a polysaccharide; a methacrylate monomer; an ultraviolet initiator; and a chemical crosslinker. Next the hydrogel precursor reactants are heated to a temperature higher than the melting point of the polysaccharide and this temperature is retained until the polysaccharide is in a sol state. Then the single-pot is cooled to a temperature lower than the gelation point of the polysaccharide and this temperature is retained to form a first network. Thereafter, photo-initiated polymerization of the methacrylate monomer occurs via the ultraviolet initiator to form the second network.

Abstract: A coordinate measuring machine has a base for supporting an object, a movable assembly having a probe for measuring the object, and a rail movably guiding the movable assembly along its length. The rail includes carbon fiber and has a rail CTE. The coordinate measuring machine also has an air bearing member circumscribing the rail and fixedly coupled with the movable assembly. The air bearing member has a member CTE, which is about equal to the rail engineered CTE.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

Abstract: An image scanner has an operation clock generator, a photoelectric converter, an AD converter configured to convert the analog pixel signals serially output by the photoelectric converter to digital pixel data by sampling the analog pixel signals in accordance with an operation clock generated by the operation clock generator, a data generator configured to generate read image data representing an read image of the original based on the pixel data converted by the AD converter, a resolution setter configured to set a reading resolution in the sub scanning direction, and a line period determiner configured to determine the line period to be (integer+decimal value) times a modulation period based on the reading resolution set by the resolution setter, the modulation period being inversion of the modulation frequency. The integer is greater than one and the decimal value is determined based on the reading resolution.

Abstract: Methods and systems for evaluating renal function of a live subject. The method includes intravenously administering nanoparticles of a noble metal to the kidney of the live subject, followed by illuminating the kidney with a near infrared excitation wavelength such that the nanoparticles in the kidney fluoresce, and finally detecting presence or absence of nanoparticle fluorescence in the kidney. Detecting presence or absence of nanoparticle fluorescence includes obtaining at least one image of the kidney through the subject's skin.

Abstract: An electrical cable connector assembly comprises a receptacle connector mated with a plug/cable connector. The receptacle connector mounted upon an external printed circuit board and includes an insulative housing forming a mating cavity, and a terminal module assembly received within the housing with contacting sections exposed in the mating cavity. The cable connector includes an internal printed circuit board with a contact module fixed at a front end region and a cable having a plurality of wires fixed at a rear end region in a multilevel manner. A die-casting cover encloses the internal printed circuit board with heat dissipation fin structure on an exterior surface.

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

Abstract: Embodiments of the present disclosure relate to a CAPTCHA generation method. According to the method, a request for accessing a resource is received from a handheld touch screen device. A default virtual keyboard type is received from the handheld touch screen device. In response to the request, a CAPTCHA is generated based on the default virtual keyboard type. The CAPTCHA is sent to the handheld touch screen device.

Abstract: Techniques for determining a position of a mobile device using visible light communication signals are provided. An example device includes memory and a processor configured to in response to a determination that at least one first image of a plurality of images stored in the memory is of a modulated light signal transmitted by a light source and comprising coded information, determine a spatial location of a reference point of the light source based on the coded information, in response to a determination that at least one second image of the plurality of images is of an unmodulated light signal emanating from the light source, determine an image location of the reference point of the light source in the at least one second image, and determine a position of the mobile wireless communication device based on the image location of the reference point and the spatial location of the reference point.