Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a plurality of photodetectors disposed within a substrate, and the plurality of photodetectors includes a first active photodetector and a black level correction (BLC) photodetector. A metal grid structure surrounds the first active photodetector along a periphery of the first active photodetector on a first side of the substrate. A recessed blocking structure covers the BLC photodetector on the first side of the substrate. The recessed blocking structure includes both a first blocking layer inset into the first side of the substrate and a second blocking layer directly over the first blocking layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first bond pad isolation structure within a substrate. A second bond pad isolation structure is formed with the substrate. The second bond pad isolation structure is disposed laterally between inner sidewalls of the first bond pad isolation structure. The first bond pad isolation structure and the second bond pad isolation structure are formed concurrently with one another. A bond pad is formed extending through the substrate. The bond pad comprises a conductive body overlying the second bond pad isolation structure and a conductive protrusion extending from the conductive body to below the substrate. The second bond pad isolation structure laterally wraps around the conductive protrusion.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a thin film resistor (TFR) with a taper profile. The semiconductor structure further includes a first contact physically contacting a first portion of the TFR. The semiconductor structure includes a second contact physically contacting a second portion of the TFR. The semiconductor structure further includes an oxide layer, over the second dielectric layer and surrounding the first contact and the second contact, and an inter-metal dielectric (IMD) layer over the oxide layer. The IMD layer is substantially free of voids and surrounds a first metal plug physically contacting the first contact and a second metal plug physically contacting the second contact.

Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a thin film resistor (TFR) layer overlying a semiconductor substrate. A first conductive structure is disposed on an outer region of the TFR layer. The first conductive structure comprises a lateral portion adjacent to a vertical portion. A height of the vertical portion is greater than a height of the lateral portion. A capping structure is disposed on a middle region of the TFR layer and abuts the vertical portion of the first conductive structure.

Abstract: A method of manufacturing a hybrid SOI substrate includes epitaxially growing a sacrificial layer and then an upper semiconductor layer over a semiconductor body. The sacrificial layer may be a heavily doped semiconductor. The heavy doping allows the sacrificial layer to be selectively etched while leaving the upper semiconductor layer largely intact. An SOI region of the semiconductor body is masked while the upper semiconductor layer and the sacrificial layer are etched from a peripheral region of the semiconductor body. A bulk semiconductor is then grown to replace the etched layers on the peripheral region. Holes are formed through the upper semiconductor layer in the SOI region and the sacrificial layer is etched from beneath the upper semiconductor. The holes may then be filled with dielectric leaving a cavity beneath the upper semiconductor layer in the SOI region.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a conductive structure disposed within a dielectric structure along a first side of a substrate. An insulating structure is disposed along inner sidewalls of the substrate and a blocking layer is disposed along a first inner sidewall and a second inner sidewall of the insulating structure, as viewed in a cross-sectional view. A through-substrate via (TSV) extends vertically through the substrate and along a horizontally-extending surface of the insulating structure. The horizontally-extending surface protrudes outward from the first inner sidewall of the insulating structure and towards the second inner sidewall of the insulating structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC). The IC includes a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate. An insulating structure is disposed along inner sidewalls of the semiconductor substrate. The inner sidewalls of the semiconductor substrate extend through the semiconductor substrate. A blocking layer is disposed along inner sidewalls of the insulating structure. A through-substrate via (TSV) includes a first portion and a second portion. The first portion extends from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure. The second portion extends from the first portion to the conductive structure and has a maximum width less than that of the first portion.

Abstract: Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a resistor layer over a substrate. An isolation structure contacts a first pair of opposing sidewalls of the first resistor layer. The isolation structure includes a body structure and a liner layer disposed on opposing sidewalls of the body structure.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a mask layer on a first side of a semiconductor substrate. The mask layer comprises a plurality of sidewalls defining a plurality of openings. A first etch process is performed on the semiconductor substrate to form a plurality of recesses within the semiconductor substrate. A second etch process is performed on the semiconductor substrate to expand the plurality of recesses and form a plurality of protrusions that comprise curved opposing sidewalls.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.

Abstract: A self-aligned plug may be formed between deep trench isolation (DTI) etching cycles. Accordingly, etch depth in areas of a pixel sensor with large CDs (e.g., at an X-road) is reduced, which prevents trench loading. As a result, a floating diffusion (FD) region, associated with photodiodes of the pixel sensor, is not damaged during the DTI etching cycles. Reduced chances of damage to the FD region improves performance of the pixel sensor and prevents electrical shorts and failures, which increases yield and conserves time and raw materials used in forming the pixel sensor.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a photodetector disposed within a substrate. A grid structure is disposed over the substrate and the photodetector. A conductive layer is disposed between the grid structure and the substrate. A conductive contact extends into an upper surface of the substrate. The conductive layer is directly electrically coupled to the conductive contact.

Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.