Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.

Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor including a dummy vertical transistor structure underlying a photodetector. The pixel sensor includes a substrate having a front-side surface opposite a back-side surface. The photodetector is disposed within the substrate. A deep trench isolation (DTI) structure extends from the back-side surface of the substrate to a first point below the back-side surface. The DTI structure wraps around an outer perimeter of the photodetector. The dummy vertical transistor structure is laterally spaced between inner sidewalls of the DTI structure. The dummy vertical transistor structure includes a dummy vertical gate electrode having a dummy conductive body and a dummy embedded conductive structure. The dummy embedded conductive structure extends from the front-side surface of the substrate to a second point vertically above the first point and the dummy conductive body extends along the front-side surface of the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond pad disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. An upper surface of the semiconductor substrate is vertically below the back-side surface. The bond pad extends through the semiconductor substrate. The bond pad includes a conductive body over the upper surface of the semiconductor substrate and conductive protrusions extending from above the upper surface to below the front-side surface of the semiconductor substrate. A vertical distance between a top surface of the bond pad and the back-side surface of the semiconductor substrate is less than a height of the conductive protrusions. A first bond pad isolation structure extends through the semiconductor substrate and laterally surrounds the conductive protrusions.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: Various embodiments of the present disclosure are directed towards a method for manufacturing a semiconductor structure. The method includes forming photodetectors within a semiconductor substrate. A charge release layer is deposited over the semiconductor substrate. A conductive contact is formed over the charge release layer such that a contact protrusion of the conductive contact extends through the charge release layer. The charge release layer is disposed along opposing sidewalls of the conductive contact. The charge release layer is electrically coupled to ground via the conductive contact.

Abstract: An optical isolation structure and a method for fabricating the same are provided. The optical isolation structure includes an epitaxial layer and a dielectric layer. The epitaxial layer and the dielectric layer are formed in a deep trench of a semiconductor substrate. The epitaxial layer covers a lower portion of sidewall of the trench, and the dielectric layer covers an upper portion of the sidewall of the trench. In the method for fabricating the optical isolation structure, at first, shallow trenches are formed in the semiconductor substrate. Then, the dielectric layer is formed in the shallow trenches. Thereafter, deep trenches are formed passing through the dielectric layers. Then, the epitaxial layer is formed in the deep trenches.

Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a pixel region formed in a substrate and a storage region formed in the substrate and adjacent to the pixel region. The FSI image sensor device structure further includes a first gate structure formed over the storage region and a metal shield structure formed over the first gate structure. The FSI image sensor device structure further includes a conductive structure formed adjacent to the first gate structure. In addition, the conductive structure is electrically connected to the metal shield structure through a via.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate having a first photodetector region and forming a gate material over the gate dielectric layer. A dielectric protection layer is deposited over the gate dielectric layer and a first sidewall spacer is formed along a side of the gate material. The dielectric protection layer extends from a first location directly over the first photodetector region to a second location between the first sidewall spacer and the gate dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductive substrate; forming a gate structure over the semiconductive substrate; forming a first dielectric layer over the gate structure; forming a first through hole in the first dielectric layer adjacent to and spaced apart from a sidewall of the gate structure; filling the first through hole with a material; forming a via in the first dielectric layer by etching the material and the first dielectric layer; removing the material to form a second through hole in the first dielectric layer; and forming a conductive structure by filling the via and the second through hole with a conductive material.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a charge release layer. A photodetector is disposed within a semiconductor substrate. An etch stop layer overlies the photodetector. A color filter overlies the etch stop layer. A dielectric grid structure surrounds the color filter. The charge release layer is sandwiched between the dielectric grid structure and the etch stop layer. The charge release layer surrounds the color filter and comprises a conductive material. The charge release layer directly contacts the color filter.

Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.

Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a light pipe structure. A photodetector disposed within a semiconductor substrate. A gate electrode is over the semiconductor substrate and borders the photodetector. An inter-level dielectric (ILD) layer overlies the semiconductor substrate. A conductive contact is disposed within the ILD layer such that a bottom surface of the conductive contact is below a top surface of the gate electrode. The light pipe structure overlies the photodetector such that a bottom surface of the light pipe structure is recessed below a top surface of the conductive contact.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.

Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.