Abstract: A field wheat stem tillering number extraction method, including: acquiring field wheat point clouds by means of a LiDAR, and extracting any row of wheat point clouds in a research area; projecting a Y axis to a plane, and retaining an X and Z axis; applying adaptive layering to obtain number of clusters of the wheat row; applying hierarchical clustering analysis to obtain tillering number of each wheat cluster; and further obtaining stem tillering number of the whole wheat row, so as to extract a field wheat stem tillering number. The feasibility of an algorithm is verified by comparing the wheat stem tillering number extracted by means of the method with an actually measured field stem tillering number, and the method realizes rapid, accurate and nondestructive extraction of a large-field crop stem tillering number and provides theoretical basis and technical support for extraction of the field wheat stem tillering number.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A memory device includes an alternating layer stack including conductive/dielectric layer pairs stacked in a first direction, a first insulating layer on the alternating layer stack, a thickness of the first insulating layer being larger than a thickness of the dielectric layer, and a channel structure extending through the alternating layer stack and the first insulating layer along the first direction. The channel structure includes an epitaxial layer disposed at a first end of the channel structure away from the first insulating layer, a functional layer on the epitaxial layer and extending along the first direction, a channel layer covering a sidewall of the functional layer and in contact with the epitaxial layer, and a filling structure covering a sidewall of the channel layer.

Abstract: Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A chip stacked structure includes a first chip and a second chip. The first chip includes a first substrate, a first functional layer, and first through silicon vias. A diameter of the first through silicon via close to the first functional layer is greater than a diameter of the first through silicon via close to the first substrate. The second chip includes a second substrate and a second functional layer. The chip stacked structure further includes a first redistribution layer disposed on a side that is of the second functional layer and that is away from the second substrate, a first dielectric layer disposed between the first substrate and the first redistribution layer, and a plurality of first bonding metal blocks disposed in the first dielectric layer.

Abstract: Embodiments of a hybrid-bonded semiconductor structure are disclosed. The semiconductor structure comprises a first conductive structure and a second conductive structure in a base dielectric layer. The base dielectric layer has a non-flat top surface. A first top surface of the first conductive structure is non-coplanar with a second top surface of the second conductive structure. The semiconductor structure further comprises an alternating dielectric layer stack comprising a plurality of dielectric layers sequentially disposed on the base dielectric layer, wherein at least two of the plurality of dielectric layers have non-uniform thickness. The semiconductor structure further comprises a first lead wire and a second lead wire formed in the alternating dielectric layer stack and electrically connected to the first conductive structure and the second conductive structure, respectively.

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a plurality of channel holes penetrating the alternating dielectric stack; forming a channel structure in each channel hole; forming a channel column structure on the channel structure in each channel hole; trimming an upper portion of each channel column structure to form a channel plug; and forming a top selective gate cut between neighboring channel plugs.

Abstract: A semiconductor device includes a peripheral circuit, a stacked structure including a first side and a second side along a vertical direction, and alternating conductive layers and first insulating layers, a memory string extending through the stacked structure, a bonding structure located between the first side of the stacked structure and the peripheral circuit in the vertical direction and connected with the memory string and the peripheral circuit, a second insulating layer located at the second side of the stacked structure; and a conductor structure located in the second insulating layer.

Abstract: The invention provides a chip stacking structure, including: a first chip, a second chip stacked with the first chip, a first redistribution layer, a second redistribution layer, a third redistribution layer, a first conductive channel, and a second conductive channel;; the first redistribution layer is disposed on a surface of the first chip facing the second chip; the second redistribution layer is disposed on a passive surface of the second chip, and the third redistribution layer is disposed on an active surface of the second chip; the first conductive channel passes through the second chip and the third redistribution layer, connecting the first redistribution layer and the second redistribution layer; and the second conductive channel passes through the second chip, connecting the second redistribution layer and the third redistribution layer.

Abstract: A chip stacking structure includes a plurality of chips that are sequentially stacked and a first redistribution layer arranged on an active side of each chip. The plurality of chips include a first chip and a second chip that are located on an outermost side. Passive sides of the first chip and the second chip both face an outer side, and the chip stacking structure further includes a second redistribution layer arranged on the passive side of the first chip or the second chip. The second redistribution layer is electrically connected to at least one first redistribution layer through a first via hole.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.

Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

Abstract: Embodiments of methods for forming a hybrid-bonded semiconductor structure are disclosed. The method include disposing first second, third, and fourth dielectric layers, forming first and second openings by etching the fourth dielectric layer using a first etching selectivity, etching the third and fourth dielectric layers in the first and second openings respectively using a second etching selectivity, etching the second and third dielectric layers in the first and second openings using the first etching selectivity, etching the first dielectric layer in the first opening and the second dielectric layer in the second opening using the second etching selectivity, etching the first dielectric layer in the first and second openings using the first etching selectivity, and forming conductive material in the first and second openings.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate and a first bonding layer on a surface of the first substrate, and the material of first bonding layer includes dielectric materials of silicon, nitrogen and carbon, and an atomic concentration of carbon in the first bonding layer gradually increases along with an increase of thickness of the first bonding layer from the surface of first substrate and reaches a maximum atomic concentration of carbon at a surface of the first bonding layer.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.