Abstract: A apparatus and method for manufacturing a photovoltaic module includes components for heating the module and applying an electrical bias to the module to improve photovoltaic module performance and manufacture multiple photovoltaic modules with similar performance.

Abstract: An inline vacuum deposition system contains thermal source pairs configured in adjacent deposition zones. Dopant sources allow the electrical characteristics of the sequentially formed layers to be controlled for a preferred deposition growth profile.

Abstract: A apparatus and method for manufacturing a photovoltaic module includes components for heating the module and applying an electrical bias to the module to improve photovoltaic module performance and manufacture multiple photovoltaic modules with similar performance.

Abstract: The present invention relates to methods for cleaning semiconductors used in photovoltaic cells and modules, and methods for manufacturing p-n junctions for photovoltaic cells and modules. More particularly, the method comprises providing at least one semiconductor layer of a photovoltaic module and scrubbing the surface of the least one semiconductor layer in the presence of a chemical solution.

Abstract: A completed photovoltaic device and method forming it are described in which fluxing of a window layer into an absorber layer is mitigated by the presence of a sacrificial fluxing layer.

Abstract: Embodiments include photovoltaic devices that include at least one absorber layer, e.g. CdTe and/or CdSxTe1-x (where 0?x?1), having an average grain size to thickness ratio from greater than 2 to about 50 and an average grain size of between about 4 ?m and about 14 ?m and methods for forming the same.

Abstract: A photovoltaic device is disclosed including at least one Cadmium Sulfide Telluride (CdSxTe1-x) layer as are methods of forming such a photovoltaic device.

Abstract: A back electrode for a PV device and method of formation are disclosed. A ZnTe material is provided over an absorber material and a MoNx material is provided over the ZnTe material. A Mo material may also be included in the back electrode above or below the MoNx layer and a metal layer may be also provided over the MoNx layer.

Abstract: Photovoltaic devices with a zinc oxide layer replacing all or part of at least one of a window layer and a buffer layer, and methods of making the devices.

Abstract: A method of installing and managing a solar module array includes determining a desired output capacity of the array, providing a first number of solar modules to generate electrical power at the desired output capacity, installing the first number of solar modules as the array at a plant site, and operating the array to generate electrical power. The array is monitored for an event that triggers providing a second number of the solar modules as recharge modules to compensate for degradation of the desired output capacity based upon at least one of a predetermined percentage of degradation and a predetermined period of operation. The array is monitored for the event over a monitoring period less than the operating life of the array to trigger further provision of the recharge modules as needed.

Abstract: A photovoltaic device including a protective layer between a window layer and an absorber layer, the protective layer inhibiting dissolving/intermixing of the window layer into the absorber layer during a device activation step, and methods of forming such photovoltaic devices.

Abstract: A photovoltaic device includes a substrate structure and a p-type semiconductor absorber layer, the substrate structure including a CdSSe layer. A photovoltaic device may alternatively include a CdSeTe layer. A process for manufacturing a photovoltaic device includes forming a CdSSe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming a p-type absorber layer above the CdSSe layer.

Abstract: A method for producing apparatus for producing and photovoltaic device including semiconductor layers with halide heat treated surfaces that increase grain growth within at least one of the semiconductor layers and improve the interface between the semiconductor layers. The halide heat treatment includes applying and heating multiple coatings of a halide compound on surfaces adjacent to or part of the semiconductor layers.

Abstract: An apparatus and a method for testing and/or conditioning photovoltaic modules. The apparatus includes a set of contacts for contacting electrical conductors of the module and a testing and/or conditioning system for testing and/or conditioning of the module and measuring parameters associated therewith.

Abstract: The present invention relates to methods for cleaning semiconductors used in photovoltaic cells and modules, and methods for manufacturing p-n junctions for photovoltaic cells and modules.

Abstract: Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.

Abstract: The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material.