Abstract: A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to within the trench. First isolation material is removed effective to form a line trench into a desired local interconnect. Conductive material is formed therewithin. A second isolation material is deposited over the first isolation material, over the conductive material within the isolation trench and within the line trench. At least some first and second isolation material is removed in at least one common removing step. Integrated circuitry includes a substrate comprising trench isolation material. A local interconnect line is received within a trench formed within the isolation material. The local interconnect includes at least two different conductive materials. One of the conductive materials lines the trench. Another of the conductive materials is received within a conductive trench formed by the one. Other implementations are disclosed.

Abstract: A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

Abstract: A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n?well conductive region and a p?well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n?well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p?well regio

Abstract: A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.

Abstract: An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

Abstract: Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers—an overlying and underlying refractory metal nitride layer—on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making and using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers-an overlying and underlying layer-on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: An intermediate semiconductor device for use in making surface channel MOS transistors is disclosed. The intermediate semiconductor device includes a semiconductor substrate having a top surface, a bottom surface, a plurality of doped isolation regions and a first surface channel. A first dielectric layer overlies a first portion of the top surface of the semiconductor substrate and a portion of at least one of the plurality of doped isolation regions. A first polysilicon layer overlies the first dielectric layer, and a second dielectric layer overlies the first polysilicon layer and a second portion of the top surface of the semiconductor substrate. The second dielectric layer is overlaid with a second polysilicon layer.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers-an overlying and underlying layer-on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: Methods for making surface channel MOS transistors.