Abstract: An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; and a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); where the pattern unit (171a) further includes a second bump (1712) located within a central area surrounded by each of the first bumps (1710), and the spacing groove (1711) on a same side of the first bump (1710) and the second bump (1712) is arranged in a non-straight shape.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).

Abstract: A pixel circuit, a display panel, a display device and a driving method. The pixel circuit includes: a first control module, a latch module, a second control module, a first input module and a second input module. The first control module provides a signal on a data line to a first node under control of a signal of first gate line. The latch module latches signals of the first node and a second node. The second control module provides signal on the data line to a third node under control of a signal on a second gate line. The first input module provides a signal of a reference signal terminal to a pixel electrode under control of signal of the first node. The second input module provides a signal of the third node to the pixel electrode under control of signal of the second node.

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: A display panel includes a second substrate. The second substrate includes a second base substrate and a shielding layer, an array structure layer, an insulating layer and a reflective layer which are sequentially disposed on a second base substrate, the array structure layer includes gate lines; the shielding layer includes a plurality of groups of light shielding units sequentially arranged along a first direction, each group of the light shielding units includes a plurality of independent sub-light shielding units sequentially arranged along a second direction, the reflective layer includes a plurality of reflective units arranged in an array, the plurality of reflective units form a plurality of reflective rows and a plurality of reflective columns, a first space area is formed between adjacent reflective columns, and a second space area is formed between adjacent reflective rows forms.

Abstract: A shift register unit, a driving method, a drive circuit, and a display apparatus are disclosed. The shift register unit includes: a control circuit, which is configured to adjust signals of a first node and a second node according to an input signal end, a first control signal end, a second control signal end and a first reference signal end; a cascade circuit, which is configured to provide, according to the signal of the first node, a signal of a first cascade clock signal end to a cascade output end; and an output circuit, which is configured to provide, according to the signal of the first node, a signal of a control clock signal end to a drive output end, and provide, according to the signal of the second node, a signal of a second reference signal end to the drive output end.

Abstract: An array substrate includes: a first substrate (10), including a plurality of sub-pixel regions (101) arranged in an array along a row direction (X) and a column direction (Y); a pixel circuit layer, including a plurality of sub-pixel circuits; a planarization layer (17), provided with a first via hole (170) located in the sub-pixel regions (101), and includes at least one pattern portion (171), the pattern portion (171) includes a plurality of pattern units (171a) arranged in an array along the row direction (X) and the column direction (Y); and a reflective electrode layer, wherein the reflective electrode layer includes a plurality of reflective electrodes (18) that are mutually disconnected, each of the reflective electrodes (18) is located in one of the sub-pixel regions (101) and is electrically connected to the sub-pixel circuit through the first via hole (170).

Abstract: The present disclosure relates to a pixel circuit. The pixel circuit may include a first pixel unit having a first display driving circuit, a first pixel, and a first control circuit, and a second pixel unit having a second display driving circuit, a second pixel electrode, and a second control circuit. The first control circuit may be configured to adjust and latch a voltage of a first positive phase node and the first display driving circuit. The first display driving circuit may be configured to provide a first display driving voltage to the first pixel electrode. The second control circuit may be configured to adjust and latch a voltage of a second positive phase node and the second display driving circuit. The second display driving circuit may be configured to provide a second display driving voltage to the second pixel electrode.

Abstract: An array substrate includes: a first substrate; a plurality of gate lines and a plurality of data lines; a plurality of thin film transistors; and a plurality of reflective electrodes. The plurality of gate lines and the plurality of data lines define a plurality of sub-pixel regions. A thin film transistor is located in a sub-pixel region. A reflective electrode is located in the sub-pixel region and electrically connected to the thin film transistor in the same sub-pixel region. Each reflective electrode has a border including a plurality of first sub-borders extending in a first direction, a plurality of second sub-borders extending in a second direction, and a plurality of chamfer borders each connecting a first sub-border and a second sub-border that are adjacent; and an intersection of extension lines of the first sub-border and the second sub-border is located outside the border of the reflective electrode.

Abstract: A display panel includes a second substrate. The second substrate includes a second base substrate and a shielding layer, an array structure layer, an insulating layer and a reflective layer which are sequentially disposed on a second base substrate, the array structure layer includes gate lines; the shielding layer includes a plurality of groups of light shielding units sequentially arranged along a first direction, each group of the light shielding units includes a plurality of independent sub-light shielding units sequentially arranged along a second direction, the reflective layer includes a plurality of reflective units arranged in an array, the plurality of reflective units form a plurality of reflective rows and a plurality of reflective columns, a first space area is formed between adjacent reflective columns, and a second space area is formed between adjacent reflective rows forms.

Abstract: The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.

Abstract: Provided are a display panel, a preparation method thereof, and a display apparatus. The display panel includes a first substrate and a second substrate disposed oppositely, and a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein the first substrate includes a black matrix layer and a color filter layer which are sequentially disposed on a first base substrate; at least one of the first substrate and the second substrate further includes a spacer; and the black matrix layer includes at least one first black matrix, and an orthographic projection of each first black matrix on the first base substrate covers an orthographic projection of the spacer on the first base substrate.

Abstract: A pixel circuit, a display panel, a display device and a driving method. The pixel circuit includes: a first control module, a latch module, a second control module, a first input module and a second input module. The first control module provides a signal on a data line to a first node under control of a signal of first gate line. The latch module latches signals of the first node and a second node. The second control module provides signal on the data line to a third node under control of a signal on a second gate line. The first input module provides a signal of a reference signal terminal to a pixel electrode under control of signal of the first node. The second input module provides a signal of the third node to the pixel electrode under control of signal of the second node.

Abstract: The present disclosure relates to a pixel circuit. The pixel circuit may include a first pixel unit having a first display driving circuit, a first pixel, and a first control circuit, and a second pixel unit having a second display driving circuit, a second pixel electrode, and a second control circuit. The first control circuit may be configured to adjust and latch a voltage of a first positive phase node and the first display driving circuit. The first display driving circuit may be configured to provide a first display driving voltage to the first pixel electrode. The second control circuit may be configured to adjust and latch a voltage of a second positive phase node and the second display driving circuit. The second display driving circuit may be configured to provide a second display driving voltage to the second pixel electrode.

Abstract: The present disclosure provides a full-reflection display substrate, a manufacturing method thereof and a full-reflection display device. The full-reflection display substrate includes: a base substrate, the base substrate including a display region and a non-display region; a signal line arranged in the display region; a bonding pin arranged in the non-display region, coupled to the signal line and bonded to a driving circuitry; a reflection layer arranged in the display region; and an etch stop pattern arranged at a same layer and made of a same material as the reflection layer, arranged in the non-display region, and at least covering a side surface of the bonding pin.

Abstract: Provided are a display panel, a preparation method thereof, and a display apparatus. The display panel includes a first substrate and a second substrate disposed oppositely, and a liquid crystal layer sandwiched between the first substrate and the second substrate, wherein the first substrate includes a black matrix layer and a color filter layer which are sequentially disposed on a first base substrate; at least one of the first substrate and the second substrate further includes a spacer; and the black matrix layer includes at least one first black matrix, and an orthographic projection of each first black matrix on the first base substrate covers an orthographic projection of the spacer on the first base substrate.

Abstract: A pixel circuit, which may include a first pixel unit having a first display driving circuit (12), a first pixel electrode (P1), and a first control circuit (11), and a second pixel unit having a second display driving circuit (22), a second pixel electrode (P2), and a second control circuit (21). The first control circuit (11) may be configured to adjust and latch a voltage of a first positive phase node (Q1) and the first display driving circuit (12). The first display driving circuit (12) may be configured to provide a first display driving voltage to the first pixel electrode (P1). The second control circuit (21) may be configured to adjust and latch a voltage of a second positive phase node (Q2) and the second display driving circuit (22). The second display driving circuit (22) may be configured to provide a second display driving voltage to the second pixel electrode (P2).

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.