Abstract: Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

Abstract: An array substrate includes a base substrate, a plurality of first signal lines extending in a first direction, a plurality of second signal lines located on a different layer from the first signal lines and extending in a second direction intersecting the first direction, and a plurality of touch signal lines extending in the second direction disposed on the base substrate. Each touch signal line includes a first touch line segment and a second touch line segment, the first touch line segment disposed on the same layer as the first signal lines, and at least partially overlapping with at least one of the second signal lines in a direction perpendicular to a surface of the base substrate, the second touch line segment disposed on a different layer from the first signal lines, and the first touch line segment electrically connected with the second touch line segment through a first via.

Abstract: A shift register circuit, a scan driving circuit, a display device and method for driving the scan driving circuit are provided. The shift register circuit includes: an input circuit for providing an active level for the first node upon receiving the active level of scan trigger signal; a trigger circuit for outputting the active level of scan trigger signal at the second node when first node is at the active level and a first clock signal is at first level; a locking circuit for locking the level of first node as inactive level when a first control signal is at the active level; and an output circuit for outputting a gate turn-on voltage during a period in which the second node is at an active level of the scan trigger signal, and outputting a voltage same as voltage of a second control signal during other periods other than the period.

Abstract: A pixel circuit and a display device are provided. The pixel circuit includes: a first inverter circuit having an input terminal connected to a first node and an output terminal connected to a second node; a second inverter circuit having an input terminal connected to the second node and an output terminal connected to a third node; a switching circuit configured to disconnect a connection between the first node and the third node when a first scanning signal is at an active level; and a control circuit configured to control a level of at least one of the first node and the second node according to a level control signal when the first scanning signal is at an active level. Based on this, it can help to avoid the output signal abnormality of the latch inside the pixel and enhance the working stability of the pixel circuit.

Abstract: The present disclosure relates to a shift register unit. The shift register unit includes a first input circuit configured to transmit a first voltage signal to a pull-up node, a pull-up circuit configured to transmit a first clock signal to a signal output terminal, a first pull-down control circuit configured to transmit a second clock signal to a pull-down node, a second pull-down control circuit configured to transmit a second voltage signal to the pull-down node, a pull-up control circuit configured to transmit the second voltage signal to the pull-up node, a pull-down circuit configured to transmit the second voltage signal to the signal output terminal, and a holding circuit configured to maintain the pull-up node at a low level and/or maintain the pull-down node at a high level under control of a second input.

Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

Abstract: Embodiments of the present disclosure provide a shift register circuitry and a driving method thereof, a gate driving circuitry, and a display device. The shift register circuitry includes an input circuit and a plurality of output circuits coupled to the input circuit. The input circuit is coupled to an input signal terminal, and is configured to, under the control of the voltage at the input signal terminal, cause the plurality of output circuits to operate. Each of the plurality of output circuits is coupled to a respective clock signal terminal and a respective output signal terminal, and is configured to operate to couple the clock signal terminal to the output signal terminal so as to output a driving signal at the output signal terminal.

Abstract: The present disclosure discloses a shift register, comprising: a first capacitor with a first terminal connected to a first pull-up node and a second terminal connected to a second pull-up node; a first thin-film transistor with a gate connected to the first pull-up node, a first electrode connected to the second pull-up node and a second electrode connected to a first clock signal input terminal; a second thin-film transistor with a gate connected to the second pull-up node, a first electrode connected to an output of the shift register, and a second electrode connected to a DC high level signal terminal; and an input control circuit The first capacitor, the first capacitor and the first thin-film transistor boost the voltage on the first pull-up node so as to make a clock signal inputted from the first clock signal input terminal pass to the second pull-up node.

Abstract: The present disclosure provides a shift register unit and a gate scanning circuit. In the shift register unit, when a first scanning pulse inputting terminal is at a first level, a voltage at a first node is pulled by a first DC voltage terminal; when a second scanning pulse inputting terminal is at the first level, the voltage at a first node is pulled by a second DC voltage terminal. In addition, each stage of the shift register unit have two scanning pulse outputting terminal. In a next period after the first scanning pulse outputting terminal outputs gate driving signals to the Nth row of pixel units, the second scanning pulse outputting terminal may output gate voltages to the (N+1)th row of pixel units.

Abstract: A shift register unit circuit is disclosed that includes a first node control circuit, a second node control circuit, and a plurality of output circuits. Each of the plurality of output circuits is connected to a respective output terminal and provides a gate drive signal to the respective output terminal. Also disclosed are a method of driving the shift register unit circuit, a gate drive circuit, and a display apparatus.

Abstract: A shift register, a gate driving circuit, a display panel and a driving method. The shift register includes: an input circuit, an output circuit, a pull-up-node pull-down circuit, a first control circuit, a second control circuit and an output pull-down circuit. The first control circuit is configured to write a fourth clock signal into a first pull-down node and write a first power voltage into a second pull-down node responsive to a first control signal, and to write the first power voltage into the first pull-down node responsive to a voltage of a pull-up node. The second control circuit is configured to write the fourth clock signal into the second pull-down node and write the first power voltage into the first pull-down node responsive to a second control signal, and to write the first power voltage into the second pull-down node responsive to the voltage of the pull-up node.

Abstract: There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register.

Abstract: A shift register and its driving method, a gate driving circuit and a display device, wherein the shift register comprises an input module (1), a reset module (2), a first control module (3), a second control module (4), a first output module (5) and a second output module (6), through which, the shift register makes the potential at the third node (C) for controlling the first output module (5) in a stable status via the first control module (3), and makes the potential at the fourth node (D) for controlling the second output module (6) in a stable status via the second control module (4), thereby achieving stability of the scanning signal outputted by the driving signal output terminal (Output) of the shift register, further reducing noise of the scanning signal outputted by the driving signal output terminal (Output), and improving stability of an output of the shift register.

Abstract: The present disclosure discloses a shift register and a method for driving the same, a gate driving circuit and a display apparatus. The shift register comprises an input module, a reset module, a first control module, a second control module, a first output module and a second output module. With cooperation among the above six modules, the shift register enables the potential at the third node for controlling the first output module to be in a stable state under the function of the first control module and enables the potential at the fourth node for controlling the second output module to be in a stable state under the function of the second control module. In this way, stability of the scanning signal output by the driving signal output end of the shift register is achieved, thereby reducing the noise in the scanning signal output by the driving signal output end, and improving the stability of the output of the shift register.

Abstract: A shift register and its driving method, a gate driving circuit and a display device, wherein the shift register comprises an input module (1), a reset module (2), a first control module (3), a second control module (4), a first output module (5) and a second output module (6), through which, the shift register makes the potential at the third node (C) for controlling the first output module (5) in a stable status via the first control module (3), and makes the potential at the fourth node (D) for controlling the second output module (6) in a stable status via the second control module (4), thereby achieving stability of the scanning signal outputted by the driving signal output terminal (Output) of the shift register, further reducing noise of the scanning signal outputted by the driving signal output terminal (Output), and improving stability of an output of the shift register.

Abstract: The present disclosure discloses a shift register and a method for driving the same, a gate driving circuit and a display apparatus. The shift register comprises an input module, a reset module, a first control module, a second control module, a first output module and a second output module. With cooperation among the above six modules, the shift register enables the potential at the third node for controlling the first output module to be in a stable state under the function of the first control module and enables the potential at the fourth node for controlling the second output module to be in a stable state under the function of the second control module. In this way, stability of the scanning signal output by the driving signal output end of the shift register is achieved, thereby reducing the noise in the scanning signal output by the driving signal output end, and improving the stability of the output of the shift register.

Abstract: There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register.