Abstract: A composite wafer may be provided by: forming a layer stack including a carrier layer, an ion implantation layer, and a transfer material layer by implanting ions into a donor wafer; forming intersecting trenches through the transfer material layer, the ion implantation layer, and an upper portion of the carrier layer; attaching the layer stack to an acceptor wafer including a stack of a handle substrate and a first dielectric oxide layer by bonding the layer stack to the first dielectric oxide layer; and cleaving the layer stack at the ion implantation layer, whereby a composite wafer including the acceptor wafer and patterned portions of the transfer material layer is formed.

Abstract: A method of a semiconductor-on-insulator structure includes the following steps. A semiconductor donor substrate is provided. A first implantation process is performed to form an exfoliation layer of the semiconductor donor substrate with a first ion concentration. A second implantation process is performed on a perimeter region of the exfoliation layer to form a high concentration region of the exfoliation layer with a second ion concentration higher than the first ion concentration. The semiconductor donor substrate is bonded to a semiconductor handle substrate, so that the exfoliation layer with the high concentration region is bonded to the semiconductor handle substrate. An annealing process is performed to separate the exfoliation layer from the rest of the semiconductor donor substrate.

Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a micro lens recessed from the top surface of a substrate. A concave area is formed between the surface of the micro lens and the top surface of the substrate. The method includes depositing a first dielectric material that fills a portion of the concave area using a spin coating process. The method includes depositing a second dielectric material that fills the remainder of the concave area and covers the top surface of the substrate using a chemical vapor deposition process. The method includes planarizing the second dielectric material. The method includes forming a bonding layer on the planarized second dielectric material and over the top surface of the substrate. The method includes bonding a semiconductor wafer to the substrate via the bonding layer.

Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

Abstract: A process includes depositing an edge fill dielectric over a first workpiece and a device disposed thereon. The edge fill dielectric is patterned so that only the edge portions remain. A second dielectric material is formed over the first workpiece, device, and edge fill dielectric. A planarization process levels the second dielectric material and the device. A bonding layer is formed thereon and a second workpiece bonded thereto by a dielectric-to-dielectric bond.

Abstract: A semiconductor package includes a first integrated circuit, a plurality of second integrated circuits, at least one adhesion layer and a molding compound. The second integrated circuits are bonded onto the first integrated circuit. The at least one adhesion layer extends between the second integrated circuits and on sidewalls of the second integrated circuits. The molding compound extends between the second integrated circuits and on the at least one adhesion layer, wherein a surface of the at least one adhesion layer facing away from the first integrated circuit is substantially coplanar with a surface of the molding compound facing away from the first integrated circuit.

Abstract: A method of forming a semiconductor structure is provided, and includes trimming a first substrate to form a recess on a sidewall of the first substrate. A conductive structure is formed in the first substrate. The method includes bonding the first substrate to a carrier. The method includes thinning down the first substrate. The method also includes forming a dielectric material in the recess and over a top surface of the thinned first substrate. The method further includes performing a planarization process to remove the dielectric material and expose the conductive structure over the top surface. In addition, the method includes removing the carrier from the first substrate.

Abstract: A method includes transferring a tool monitoring device over a load port of a tool. A bottom of the tool monitoring device has a plurality of holes, and the load port comprises a plurality of pins at a top surface of the load port. The tool monitoring device is placed on the top surface of the load port. The pins at the top surface of the load port are plugged into the holes of the tool monitoring device. Heights of the pins are sensed to identifying a type of the load port after the tool monitoring device is placed on the top surface of the load port. An environment around the load port is monitored by using the tool monitoring device.

Abstract: A die stacking structure, a semiconductor package and a method for forming the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; and a stack of dielectric layers, extending in between the second device dies, and laterally enclosing each of the second device dies. The dielectric layers are respectively formed of a spin-on-glass (SOG) or a polymer, and a lower one of the dielectric layers has a thickness greater than a thickness of another one of the dielectric layers at a higher level.

Abstract: A die stacking structure, a semiconductor package and a method for manufacturing the die stacking structure are provided. The die stacking structure includes a first device die; second device dies, bonded onto the first device die, and arranged side-by-side; a gap profile modifier, laterally enclosing bottommost portions of the second device dies, wherein a thickness of the gap profile modifier gradually decreases away from sidewalls of the second device dies; and a dielectric material, covering the gap profile modifier and laterally surrounding the second device dies.

Abstract: A method includes transferring a tool monitoring device to a load port of a tool. An environmental parameter of the load port is monitored by the tool monitoring device. The tool monitoring device is removed from the load port after the environmental parameter of the load port is monitored. A door of the tool in front of the load port is closed. The door of the tool is kept closed during a period from a time of transferring the tool monitoring device to the load port to a time of removing the tool monitoring device from the load port.

Abstract: An ion implantation system includes an ion implanter containing an ion source unit and a dopant source gas supply system. The system includes a dopant source gas storage tank inside a gas box container located remotely to the ion implanter and a dopant source gas supply pipe configured to supply a dopant source gas from the dopant source gas storage tank to the ion source unit. The dopant source gas supply pipe includes an inner pipe, an outer pipe enclosing the inner pipe, a first pipe adaptor coupled to first end of respective inner and outer pipes, and a second pipe adaptor coupled to seconds end of respective inner and outer pipes opposite the first end. The first pipe adaptor connects the inner pipe to the dopant source gas storage tank and the second pipe adaptor connects the inner pipe to the ion source unit.

Abstract: A method includes transferring a tool monitoring device to a load port of a tool. An environmental parameter of the load port is monitored by the tool monitoring device. The tool monitoring device is removed from the load port after the environmental parameter of the load port is monitored. A door of the tool in front of the load port is closed. The door of the tool is kept closed during a period from a time of transferring the tool monitoring device to the load port to a time of removing the tool monitoring device from the load port.

Abstract: In some embodiments, a system for monitoring a tool is provided. The system includes a tool monitoring device, a transporting system and an external apparatus. The tool monitoring device is configured to monitor an environmental parameter of a load port of a tool. The tool monitoring device includes a wafer pod and a monitoring module disposed in the wafer pod. The monitoring module includes at least one sensor, a computer coupled to the at least one sensor, a power supply electrically coupled to the at least one sensor and the computer, and a wireless unit coupled to the computer. The transporting system is configured to transfer the tool monitoring device from one load port to another load port. The external apparatus is coupled to the tool monitoring device.

Abstract: An ion implantation system includes an ion implanter containing an ion source unit and a dopant source gas supply system. The system includes a dopant source gas storage tank inside a gas box container located remotely to the ion implanter and a dopant source gas supply pipe configured to supply a dopant source gas from the dopant source gas storage tank to the ion source unit. The dopant source gas supply pipe includes an inner pipe, an outer pipe enclosing the inner pipe, a first pipe adaptor coupled to first end of respective inner and outer pipes, and a second pipe adaptor coupled to seconds end of respective inner and outer pipes opposite the first end. The first pipe adaptor connects the inner pipe to the dopant source gas storage tank and the second pipe adaptor connects the inner pipe to the ion source unit.

Abstract: A method for fault detection in a fabrication tool is provided. The method includes processing a semiconductor wafer in a fabrication tool according to a plurality of process events of a process run. The method further includes measuring humidity in the fabrication tool in at least one of the process events. The method also includes comparing the humidity measured in one of the process events with an expected humidity associated with the process event. In addition, the method includes based on the comparison, indicating an alarm condition when a difference between the measured humidity and the expected humidity exceeds a range of acceptable values associated with the process event.

Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.

Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.

Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.