Abstract: An apparatus for doping a melt of semiconductor or solar-grade material is provided. The apparatus includes a seed chuck, a seed crystal connected to the seed chuck, and a dopant container connected to the seed chuck. The seed chuck defines a first end of the apparatus, and the seed crystal defines a second end of the apparatus. The seed crystal is configured to initiate crystal growth when placed in contact with the melt. The dopant container is positioned between the first end and the second end of the apparatus, and defines a reservoir for holding dopant therein. The dopant container is configured to dispense liquid dopant into the melt when positioned proximate the melt. The dopant container and the seed crystal are connected to the seed chuck simultaneously.

Abstract: A method for bonding a first silicon part to a second silicon part includes arranging the first silicon part and the second silicon part in direct physical contact on a surface in a thermal insulating structure; controlling pressure in the thermal insulating structure to a predetermined pressure; controlling temperature in the thermal insulating structure to a predetermined temperature using one or more heaters; and bonding the first silicon part and the second silicon part during a process period. The predetermined temperature is in a temperature range that is greater than or equal to 1335° C. and less than 1414° C.

Abstract: A method for creating and using an assembly includes arranging a bonding material between a first component and a second component. The first component, the bonding material and the second component are heated to a predetermined temperature for a predetermined period to melt the bonding material and to create an assembly. The predetermined temperature is at or greater than a melting temperature of the bonding material and less than a melting temperature of the first component and the second component. The method includes using the assembly inside a batch furnace of a substrate processing system or a processing chamber of a substrate processing system. The first component and the second component are made from a material selected from a group consisting of silicon and silicon carbide. The bonding material is selected from a group consisting of aluminum, gold, germanium, indium or an alloy of silicon and aluminum, gold, germanium, or indium.

Abstract: A method for bonding a first silicon part to a second silicon part includes arranging the first silicon part and the second silicon part in direct physical contact on a surface in a thermal insulating structure; controlling pressure in the thermal insulating structure to a predetermined pressure; controlling temperature in the thermal insulating structure to a predetermined temperature using one or more heaters; and bonding the first silicon part and the second silicon part during a process period. The predetermined temperature is in a temperature range that is greater than or equal to 1335° C. and less than 1414° C.

Abstract: Production of silicon ingots in a crystal puller that involve reduction of the erosion rate at the crucible contact point are disclosed.

Abstract: Production of silicon ingots in a crystal puller that involve reduction in the formation of silicon deposits on the puller exhaust system are disclosed.

Abstract: This disclosure discloses a constant-temperature controlled circuit for an electric heating device, comprises an AC/DC switching circuit, a heating strip and a temperature controlled circuit; the heating strip comprises a heating line, a temperature sensing line and a NTC layer located between the heating line and the temperature sensing line; the temperature controlled circuit comprises a central processing unit, a voltage sampling circuit, a TRIAC circuit and a load detection circuit. Compared with existing technology, in the heating process, resistance of the NTC layer decreases as the temperature increases, since the heating strip and the voltage sampling circuit are connected in series, the output sample voltage of the voltage sampling circuit reflects the current temperature, and then the central processing unit outputs controls to switch the TRIAC circuit on or off according to the sample voltage, keeping the device at a constant temperature. Constant temperature control is realized.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.

Abstract: A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm2. Wafers sliced from the cast silicon crystalline ingot have solar cell efficiency of at least 17.5% and light induced degradation no greater than 0.2%.

Abstract: A method of preparing a silicon melt in a crucible for use in the manufacture of cast silicon, wherein the crucible comprises an opening, an opposing bottom surface, and at least one sidewall joining the opening and the bottom surface. The method comprises charging a silicon spacer to the bottom surface of the crucible; arranging a monocrystalline silicon seed crystal on the silicon spacer such that no surface of the monocrystalline silicon material is in contact with the bottom surface of the crucible; charging polycrystalline silicon feedstock to the crucible; and applying heat through at least one of the opening and the at least one sidewall in order to form a partially melted charge of silicon in the crucible.

Abstract: A crystal is sublimation grown in a crucible by way of a temperature gradient in the presence of between 1 and 200 Torr of inert gas. The pressure of the inert gas is then increased to between 300 and 600 Torr, while the temperature gradient is maintained substantially constant. The temperature gradient is then reduced and the temperature in the crucible is increased sufficiently to anneal the crystal. Following cooling and removal from the crucible, the crystal is heated in the presence of oxygen in an enclosure to a temperature sufficient to remove unwanted material from the crystal. Following cooling and removal from the enclosure, the crystal surrounded by another instance of the source material is heated in a crucible in the presence 200 and 600 Torr of inert gas to a temperature sufficient to anneal the crystal.

Abstract: The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

Abstract: In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.

Abstract: Adsorbed gaseous species and elements in a carbon (C) powder and a graphite crucible are reduced by way of a vacuum and an elevated temperature sufficient to cause reduction. A wall and at least one end of an interior of the crucible is lined with C powder purified in the above manner. An Si+C mixture is formed with C powder purified in the above manner and Si powder or granules. The lined crucible is charged with the Si+C mixture. Adsorbed gaseous species and elements are reduced from the Si+C mixture and the crucible by way of a vacuum and an elevated temperature that is sufficient to cause reduction but which does not exceed the melting point of Si. Thereafter, by way of a vacuum and an elevated temperature, the Si+C mixture is caused to react and form polycrystalline SiC.

Abstract: An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side.

Abstract: The invention relates to substrates of semi-insulating silicon carbide used for semiconductor devices and a method for making the same. The substrates have a resistivity above 106 Ohm-cm, and preferably above 108 Ohm-cm, and most preferably above 109 Ohm-cm, and a capacitance below 5 pF/mm2 and preferably below 1 pF/mm2. The electrical properties of the substrates are controlled by a small amount of added deep level impurity, large enough in concentration to dominate the electrical behavior, but small enough to avoid structural defects. The substrates have concentrations of unintentional background impurities, including shallow donors and acceptors, purposely reduced to below 5·1016 cm?3, and preferably to below 1·1016 cm?3, and the concentration of deep level impurity is higher, and preferably at least two times higher, than the difference between the concentrations of shallow acceptors and shallow donors.