Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.

Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

Abstract: An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.

Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.

Abstract: A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

Abstract: A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.

Abstract: An apparatus for controlling an output voltage of a switching mode power supply (SMPS) by adjusting a switching duty ratio is provided. A comparator outputs a state signal varying depending on a comparison result between an output voltage of the SMPS and a reference voltage. A clock generator generates an internal chip operating frequency and a switching frequency of the SMPS. A digital controller determines on/off of current cells depending on the state signal input from the comparator. A digital pulse width modulator (DPWM) determines a duty ratio of a digital pulse width modulation signal by determining a charging/discharging time of an internal capacitor based on an amount of current of the current cell.

Abstract: An apparatus for controlling an output voltage of a switching mode power supply (SMPS) by adjusting a switching duty ratio is provided. A comparator outputs a state signal varying depending on a comparison result between an output voltage of the SMPS and a reference voltage. A clock generator generates an internal chip operating frequency and a switching frequency of the SMPS. A digital controller determines on/off of current cells depending on the state signal input from the comparator. A digital pulse width modulator (DPWM) determines a duty ratio of a digital pulse width modulation signal by determining a charging/discharging time of an internal capacitor based on an amount of current of the current cell.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Abstract: A charge pump and method of operation are provided. The charge pump includes a first boosting unit configured to receive a pre-charge voltage and electrically charge a first MOS capacitor during a pre-charge period, and to boost a voltage of a connection node to a first output voltage during a boosting operation period, and a second boosting unit configured to receive the pre-charge voltage and electrically charge a second MOS capacitor during the pre-charge period, and to receive the first output voltage and boost a voltage of an output node to a second output voltage during the boosting operation period. Here, the pre-charge voltage is applied to electrically charge a parasitic capacitor during a parasitic capacitor charging period between the pre-charge period and the boosting operation period.